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SAKSHAM SHARMA

Member since: 3 years

Educational Institution: GLA University, Mathura

Country: India

Basic gates using NAND Gate

Basic gates using NAND Gate
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Counters

Counters
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Half Adder

Half Adder
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SR Flip-flop

SR Flip-flop
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Full Adder

Full Adder
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JK Flip-flop

JK Flip-flop
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D flip-flop

D flip-flop
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T flip-flop

T flip-flop
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4-bit Binary Adder (using Full Adder).

4-bit Binary Adder (using Full Adder).
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4-bit Binary Adder (using gates)

4-bit Binary Adder (using gates)
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4-bit Binary Adder/Subtractor (using gates)

4-bit Binary Adder/Subtractor (using gates)
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Basic Gates using NOR Gate

Basic Gates using NOR Gate
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Synchronous Counter

Synchronous Counter
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Bread Board Implementation of 4-Bit Binary Adder

Bread Board Implementation of 4-Bit Binary Adder
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4-bit Binary Adder

4-bit Binary Adder
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4-Bit Adder

4-Bit Adder
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Adders

Adders
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Circuit Diagram (double digit)

Circuit Diagram (double digit)
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Synchronous Counter

Synchronous Counter
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SAKSHAM SHARMA is not a collaborator of any project.

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