Member since: 3 years
Educational Institution: Not Entered
Country: Not Entered
16 : 1 Multiplexer
16 : 1 Multiplexer16 : 1 Multiplexer
16 : 1 Multiplexer8:1 MUX using 2:1 MUX
8:1 MUX using 2:1 MUX8:1 mux using 2:1mux
8:1 mux using 2:1mux4-bit right shift register
4-bit right shift registerDesign 1 bit comparator using 4:1 MUX
Design 1 bit comparator using 4:1 MUXDesign 1 bit comparator using 4:1 MUX
Design 1 bit comparator using 4:1 MUXDesign 1 bit comparator using 4:1 MUX
Design 1 bit comparator using 4:1 MUXVARUN PANDEY 1 BIT COMPARATOR USING 4:1 Mux
VARUN PANDEY 1 BIT COMPARATOR USING 4:1 MuxVARUN PANDEY 1 bit comparator using 4:1 mux
VARUN PANDEY 1 bit comparator using 4:1 muxlol
lolnand and nor
nand and nornand and nor
nand and norDEMUX
DEMUXVARUN PANDEY HW 3 DEMUX
VARUN PANDEY HW 3 DEMUXaryan khare task 4
aryan khare task 4VARUN PANDEY 2:4 decoder using SOP equation
VARUN PANDEY 2:4 decoder using SOP equationVARUN PANDEY 2:4 DECODER USING NOR LOGIC
VARUN PANDEY 2:4 DECODER USING NOR LOGICvarun task3
varun task3VARUN PANDEY 4:1 MUX USING 2:1 MUX
VARUN PANDEY 4:1 MUX USING 2:1 MUXVARUN PANDEY 16:1 MUX using 2:1 MUX
VARUN PANDEY 16:1 MUX using 2:1 MUXVARUN PANDEY IMPLEMENT USING NOR
VARUN PANDEY IMPLEMENT USING NORVARUN PANDEY Design the internal structure
VARUN PANDEY Design the internal structureCAT: USING DECODER , DESIGN THE CLC
CAT: USING DECODER , DESIGN THE CLCBCD to excess 3 code using 1:8 DEMUX
BCD to excess 3 code using 1:8 DEMUXVARUN PANDEY IMPLEMENT THE EQUATION USING DECODER
VARUN PANDEY IMPLEMENT THE EQUATION USING DECODERVARUN PANDEY IMPLEMENT FROM DECODER
VARUN PANDEY IMPLEMENT FROM DECODERHOT QUESTION VARUN PANDEY
HOT QUESTION VARUN PANDEYHW 3 CIRCUIT IMPLEMENTATION
HW 3 CIRCUIT IMPLEMENTATION1 bit comparator using 4:1 mux
1 bit comparator using 4:1 muxVARUN PANDEY 2 INPUT NAND/NOR
VARUN PANDEY 2 INPUT NAND/NORVARUN PANDEY DUAL MUX
VARUN PANDEY DUAL MUX1 bit comparator using 1:4 demux
1 bit comparator using 1:4 demuxVARUN PANDEY 2:4 DECODER USING POS EQUATION
VARUN PANDEY 2:4 DECODER USING POS EQUATION16:1 mux using 2:1 mux
16:1 mux using 2:1 muxVARUN PANDEY BCD-excess 3 code
VARUN PANDEY BCD-excess 3 codeCAT: design the internal structure of Circuit given using NAND gates.
CAT: design the internal structure of Circuit given using NAND gates.CAT. : IMPLELEMENT FROM DECODER
CAT. : IMPLELEMENT FROM DECODERCAT: IMPLEMENT USING NOR LOGIC
CAT: IMPLEMENT USING NOR LOGICCAT: implement the equation using decoder
CAT: implement the equation using decoderVARUN PANDEY 16:1 MUX USING 8:1 MUX, 8:1 MUX using 4:1 and 2:1
VARUN PANDEY 16:1 MUX USING 8:1 MUX, 8:1 MUX using 4:1 and 2:1varun task3
varun task3Design 1 bit comparator using 4:1 MUX
Design 1 bit comparator using 4:1 MUXDesign 1 bit comparator using 4:1 MUX
Design 1 bit comparator using 4:1 MUXVARUN PANDEY 1 BIT COMPARATOR USING 1:4 DEMUX
VARUN PANDEY 1 BIT COMPARATOR USING 1:4 DEMUXDesign 1 bit comparator using 4:1 MUX
Design 1 bit comparator using 4:1 MUXDesign 1 bit comparator using 4:1 MUX
Design 1 bit comparator using 4:1 MUXVARUN PANDEY 20MIC0139 DLCD LAB FAT IMPLEMENTED CIRCUIT
VARUN PANDEY 20MIC0139 DLCD LAB FAT IMPLEMENTED CIRCUITBCD to Excees-3 Converter circuit
BCD to Excees-3 Converter circuit4 ->1 multiplexer using 2->1 Multiplexers
4 ->1 multiplexer using 2->1 MultiplexersDesign 1 bit comparator using 4:1 MUX
Design 1 bit comparator using 4:1 MUXBCD to excess 3 code using 1:8 DEMUX
BCD to excess 3 code using 1:8 DEMUXVARUN PANDEY TASK 1 POS 4:16 DECODER
VARUN PANDEY TASK 1 POS 4:16 DECODER1 bit comparator using 1:4 demux
1 bit comparator using 1:4 demuxVARUN PANDEY DECODER USING REG NUMBER
VARUN PANDEY DECODER USING REG NUMBERVARUN PANDEY CLC
VARUN PANDEY CLCvarun pandey right shift register using D FF
varun pandey right shift register using D FFVARUN PANDEY 1 BIT COMPARATOR USING 1:4 DEMUX
VARUN PANDEY 1 BIT COMPARATOR USING 1:4 DEMUX