project.name

Arghya Chaudhuri_20220PHY001

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

three bit ripple down counter

three bit ripple down counter
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ArghyaChaudhuri_20220PHY001

ArghyaChaudhuri_20220PHY001
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20220PHY001 _ Arghya Chaudhuri EXAM 1

20220PHY001 _ Arghya Chaudhuri EXAM 1
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20220PHY001 _ Arghya Chaudhuri EXAM 2

20220PHY001 _ Arghya Chaudhuri EXAM 2
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4X1 MULTIPLEXER

4X1 MULTIPLEXER
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ROM

ROM
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IMPLEMENTATION BY 4X1

IMPLEMENTATION BY 4X1
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PLA

PLA
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PAL

PAL
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ArghyaChaudhuri_20220PHY001

ArghyaChaudhuri_20220PHY001
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ArghyaChaudhuri_20220PHY001 v

ArghyaChaudhuri_20220PHY001 v
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SR LATCH WITH NAND

SR LATCH WITH NAND
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SR LATCH WITH NOR

SR LATCH WITH NOR
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SR LATCH WITH CONTROL INPUT

SR LATCH WITH CONTROL INPUT
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D FLIPFLOP

D FLIPFLOP
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20220PHY001_ARGHYA CHAUDHURI

20220PHY001_ARGHYA CHAUDHURI
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HALF SUBTRACTOR

HALF SUBTRACTOR
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FULL SUBTRACTOR

FULL SUBTRACTOR
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20220PHY001_Arghya Chaudhu

20220PHY001_Arghya Chaudhu
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Encoder

Encoder
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sequential circuit with jk

sequential circuit with jk
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BCD ripple counter

BCD ripple counter
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BCD TO EXCESS 3 CODE

BCD TO EXCESS 3 CODE
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ROM IMPLEMENTATION

ROM IMPLEMENTATION
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Arghya Chaudhuri_20220PHY001 is not a collaborator of any project.

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