JK flipflop

BCD to excess three converter

3 to 8 line decoder

Implement full cicuit with decoder and two OR gate

Design a 8 to 3 line encoder

4 bit down counter

BCD to 7 segment decoder ABHISHEK KATIYAR 20220MAT001

F(x,y,z)=xy'+xz'+yz

T flip flop using NAND gates

NOT GATE

OR GATE

AND GATE

OR gate using NAND gate only

AND gate using NAND gate only

NOT gate using NAND gate

4 to 1 MUX

MULTIPLEXER

32:4 ROM

Logic Controller#1

Logic Controller#1

Assingment 5

PLA Implementation

PAL implementation

OR gate using only NOR gate

XOR gate using basic gates

XNOR gate using simple gates

AND gate using NOR gate

NOT gate using NOR gate

F(x,y,z)=xy'+xz'+yz

XOR gate using basic gates

question 7

implement by using nor gate only

OR GATE

OR GATE

OR GATE

OR GATE

OR GATE

half adder

half substractor

full adder

full adder 1

magnitude comparator

JK flip flop using AND and NOR gates

JK flip flop using AND and NOR gate

D flip flop using NAND gate

SR latch using NAND gate

SR latch using NOR gates

Master slave JK flip flop

D flipflop

AFD

RS flipflop

T flipflop

simplified expression of function F(w,x,y,z)=wxy'+xz'+yz

OR GATE

Implement FULL SUBSTRACTOR using decoder

OR GATE

Logic Controller#1