parallel adder

jk circuit excitation

3 to 8 line decoder

D Flip Flop

Full adder using decoder and two OR gates

Half-Subtractor

XOR using basic gates

PLA with 3 inputs

PAL

4 TO 1 MUX

NOT Gate

question 7

OR using NOR

Full-adder

T flip flop using nand

JK excitation circuit

D excitation circuit

T excitation circuit

NOT using NAND

AND Gate

Question 4

Full-subtractor

Full subtractor using decoder

4 TO 1 MUX OF F

J K Flipflop

OR Gate

Half-adder

AND unsing NAND

OR using NAND

AND using NOR

question 6

MAGNITUDE COMPARATOR

SR latch using nand gates

J K Flipflop using AND and NOR

SR latch using NOR gates

32 x 4 ROM

XNOR using basic gates

combinational circuit using ROM that accepts 2 bit number and generates output binary number equal to the square of the input number

NOT using NOR

BCD to excess 3 code converter

4 to 1 MUX

RS excitation circuit

SR latch with control input using NAND gates

8 to 3 line encoder

JK master slave flip flop