Gated SR latch

4 bit full adder

LAB 7

LAB_08

LAB 7

Project_DLD

Lab #03(NOR and NAND)

LAB 7

Lab_06(Full_Adder & Half_Adder)

LAB_08

Lab_09

3:8 DECODER

CircuitVerse 3-bit adder

3 bit adder

Lab_09

3 full adder with 3 bit input, and 4 bit output

4bit full adder

Lab_01

XOR USING NOR GATE

3-8 Decoder

2*4 Decoder

3-8 Decoder

3:8 DECODER

LAB_08

LAB_08

(Encoder--PriorityEncoder)Lab_09

Gated SR Latch

Untitled

2-Bit Calculator

2*4 Decoder

LAB 7

4 - Bit Adder

2*4 Decoder

Lab_09

3 Bit and Full Adder

Flip-Flops using NAND Gate

Project_DLD

(Encoder--PriorityEncoder)Lab_09

(Encoder--PriorityEncoder)Lab_09

D-Latch

4 bit full adder

3 full adder with 3 bit input, and 4 bit output

Lab_03(XOR and XNOR)