PAVITHRA P
Member since: 3 years
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EXPERIMENT No_6_ 8-BIT ODD / EVEN PARITY CHECKER/GENERATOR
EXPERIMENT No_6_ 8-BIT ODD / EVEN PARITY CHECKER/GENERATOR
Public
EXPERIMENT NO_1_ STUDY OF LOGIC GATES
EXPERIMENT NO_1_ STUDY OF LOGIC GATES
Public
EXPERIMENT NO_3_DESIGN OF ADDER AND SUBTRACTOR
EXPERIMENT NO_3_DESIGN OF ADDER AND SUBTRACTOR
Public
EXPERIMENT NO_5 _DESIGN AND IMPLEMENTATION OF CODE CONVERTORS
EXPERIMENT NO_5 _DESIGN AND IMPLEMENTATION OF CODE CONVERTORS
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ENCODER
ENCODER
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D FLIP FLOP
D FLIP FLOP
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DECODER
DECODER
Public
T FLIP FLOP
T FLIP FLOP
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JK FLIP FLOP
JK FLIP FLOP
Public
3-BIT_SYNCHRONOUS_UP COUNTER
3-BIT_SYNCHRONOUS_UP COUNTER
Public
EXPERIMENT NO_7_DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR
EXPERIMENT NO_7_DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR
Public
EXPERIMENT_NO_8_DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER
EXPERIMENT_NO_8_DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER
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EXPERIMENT_2_VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES
EXPERIMENT_2_VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES
Public
EXPERIMENT_10_SYNCHRONOUS UP/DOWN COUNTER
EXPERIMENT_10_SYNCHRONOUS UP/DOWN COUNTER
Public
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