project.name

Srinithi S

Member since: 3 years

Educational Institution: SRI SAIRAM ENGINEERING COLLEGE

Country: India

JK flip flop

JK flip flop
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3 bit Asynchronous counter

3 bit Asynchronous counter
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3 bit odd parity checker

3 bit odd parity checker
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logic gates

logic gates
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Multiplexer

Multiplexer
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Demultiplexer

Demultiplexer
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Code convertors

Code convertors
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logic gates

logic gates
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Design of adder and subtractor

Design of adder and subtractor
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2 bit magnitude comparator

2 bit magnitude comparator
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2 bit magnitude comparator

2 bit magnitude comparator
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3 bitsynchronous upcounter

3 bitsynchronous upcounter
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D flip flop

D flip flop
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2 bit magnitude comparator

2 bit magnitude comparator
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Magnitude comparator

Magnitude comparator
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Parity Checker

Parity Checker
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year 2021:)

year 2021:)
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Decoder

Decoder
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Magnitude comparator

Magnitude comparator
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4-Bit adder

4-Bit adder
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Encoder

Encoder
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SR Flip FLop

SR Flip FLop
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T Flip Flop

T Flip Flop
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Design of adder and subtractor

Design of adder and subtractor
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DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER

DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER
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BOOLEAN FUNCTIONS

BOOLEAN FUNCTIONS
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