project.name

Vasagiri_Divija 18BEC0911

Member since: 3 years

Educational Institution: VIT vellore

Country: Not Entered

question 4

question 4
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QUESTION 5

QUESTION 5
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task5_demux

task5_demux
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task5_demux

task5_demux
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7Seg_using_3:8Dec

7Seg_using_3:8Dec
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task5_demux_3

task5_demux_3
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7 segment display hex

7 segment display hex
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Task5_demux2

Task5_demux2
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Task5 NAND

Task5 NAND
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QUESTION 6

QUESTION 6
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7Seg_using_4:16Dec

7Seg_using_4:16Dec
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SR latch

SR latch
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Untitled

Untitled
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Task5_demux2

Task5_demux2
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task5_demux_3

task5_demux_3
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Task 5

Task 5
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7_SEGMENT_DISPLAY_DECODER_18BEC0911

7_SEGMENT_DISPLAY_DECODER_18BEC0911
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Untitled

Untitled
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7_SEGMENT_DISPLAY_DECODER_18BEC0911

7_SEGMENT_DISPLAY_DECODER_18BEC0911
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TASK4_18BEC0911_17

TASK4_18BEC0911_17
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