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Md Yasin

Member since: 3 years

Educational Institution: Techno India University

Country: India

Exp 8B : Even/Odd Parity Generator Circuit

Exp 8B : Even/Odd Parity Generator Circuit
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Exp 5 : Half Adder and Full Adder Circuit

Exp 5 : Half Adder and Full Adder Circuit
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Exp 7A : 4x1 Multiplexer Circuit

Exp 7A : 4x1 Multiplexer Circuit
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MOD-12 Ripple Up Counter

MOD-12 Ripple Up Counter
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Tic tac toe Simulator

Tic tac toe Simulator
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Exp 7B: 3-to-8 Decoder Circuit

Exp 7B: 3-to-8 Decoder Circuit
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8 X 1 MULTIPLEXER

8 X 1 MULTIPLEXER
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Full Subtractor using 3x8 Decoder

Full Subtractor using 3x8 Decoder
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Exp 9B : Realization of JK Flip flop using Universal Gate

Exp 9B : Realization of JK Flip flop using Universal Gate
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Q. Implement F(P,Q,R,S) = ∑m(1,4,6,9,12,14) using gate.

Q. Implement F(P,Q,R,S) = ∑m(1,4,6,9,12,14) using gate.
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EXP 3: Familiarization with Exclusive Gate

EXP 3: Familiarization with Exclusive Gate
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Exp 4 : Binary to Gray Conversion and vice versa

Exp 4 : Binary to Gray Conversion and vice versa
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Exp 6: Half Subtractor and Full Subtractor Circuit

Exp 6: Half Subtractor and Full Subtractor Circuit
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Exp 8A: Study of 1-bit Magnitude Compactor

Exp 8A: Study of 1-bit Magnitude Compactor
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Exp 9A: Familiarization with SR and D flip Flop

Exp 9A: Familiarization with SR and D flip Flop
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ASYNCHRONOUS MOD 12 COUNTER

ASYNCHRONOUS MOD 12 COUNTER
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