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Anirudh S Priyan/Cycle 2 - Experiment3
Anirudh S Priyan/Cycle 2 - Experiment3Cycle 2 Experiment 4
Cycle 2 Experiment 4Cycle 2 Expt 4- D flip flop
Cycle 2 Expt 4- D flip flopCycle2 Expt4- T flipflop
Cycle2 Expt4- T flipflopCycle 2 expt 4- JK
Cycle 2 expt 4- JKCycle2_Expt3
Cycle2_Expt3Multiplexer-Cycle2-expt2
Multiplexer-Cycle2-expt2Demux-Cycle2-Expt2
Demux-Cycle2-Expt2Cycle 2 Experiment 5 Ring Counter
Cycle 2 Experiment 5 Ring CounterUntitled
UntitledFULL_ADDER_BASIC_GATES
FULL_ADDER_BASIC_GATESFULL_ADDER_UNIVERSAL_GATE
FULL_ADDER_UNIVERSAL_GATEHALF_ADDER_BASIC GATES
HALF_ADDER_BASIC GATESHALF_SUBTRACTOR_BASIC_GATES
HALF_SUBTRACTOR_BASIC_GATESHALF_SUBTRACTOR_UNIVERSAL_GATE
HALF_SUBTRACTOR_UNIVERSAL_GATEFULL_SUBTRACTOR_BASIC_GATES
FULL_SUBTRACTOR_BASIC_GATESFULL_SUBTRACTOR_UNIVERSAL_GATE
FULL_SUBTRACTOR_UNIVERSAL_GATECycle 2 Experiment 5 Shift register
Cycle 2 Experiment 5 Shift registerUntitled
UntitledUntitled
UntitledCycle2 Expt7 4 bit up counter
Cycle2 Expt7 4 bit up counterCycle 2 Experiment 7 (1-3-5-7 counter)
Cycle 2 Experiment 7 (1-3-5-7 counter)HALF_ADDER_UNIVERSAL_GATE
HALF_ADDER_UNIVERSAL_GATECycle 2 Experiment 5 Johnson Counter
Cycle 2 Experiment 5 Johnson CounterCycle 2 Experiment 7-Mod 7 Up Counter
Cycle 2 Experiment 7-Mod 7 Up Counter