Member since: 3 years
Educational Institution: VIT Vellore
Country: India
Decoder-VIVA2
Decoder-VIVA2cat2-q3-b
cat2-q3-b4:16 decoder using 3:8
4:16 decoder using 3:8F = (ABC)+(A'B'CD)+(ABC'D')+(BD)
F = (ABC)+(A'B'CD)+(ABC'D')+(BD)Untitled
UntitledHalf Adder using Decoder
Half Adder using Decoderreg Decoder
reg DecoderAdders using decoders
Adders using decodersMUX VIVA1
MUX VIVA1Viva--3--or-and
Viva--3--or-and8:1MUX--XS-3--to--gray
8:1MUX--XS-3--to--gray4:16 Decoder internal
4:16 Decoder internalTASK-1
TASK-1trrstrss
trrstrssHW-5 == 10 input NAND gate using 2 input NAND
HW-5 == 10 input NAND gate using 2 input NANDUntitled
Untitledbcd to xs3 using 8:1 de-mux
bcd to xs3 using 8:1 de-muxcat-1 q2
cat-1 q2fat lab
fat labVIVA-3
VIVA-3task-3 --q-1
task-3 --q-1decoder
decoderUntitled
Untitledtask-3--2
task-3--2TASK5
TASK5cat 2 q1 a
cat 2 q1 aTask-3-1
Task-3-1Task3
Task3MUX VIVA1
MUX VIVA1VIVA-4 -- AND & OR
VIVA-4 -- AND & OR4:16 DECODER USING 2:4 DECODER
4:16 DECODER USING 2:4 DECODER16:1
16:18:1
8:14:16 decoder using 3:8 Active high SOP and POS using 3:8 decoder:
4:16 decoder using 3:8 Active high SOP and POS using 3:8 decoder:VIVA 5 HW NAND \ NOR GATES
VIVA 5 HW NAND \ NOR GATES1:8 Demux using 1:2 Demux
1:8 Demux using 1:2 DemuxRing counter
Ring counter2's Complement
2's ComplementTask2
Task24 input nand gate
4 input nand gateDecoder-VIVA2
Decoder-VIVA23:8 Decoder
3:8 DecoderXS-3 to Gray using decoder
XS-3 to Gray using decoderRing and Johnson Counter
Ring and Johnson Counter4:16 decoder using 2:4 decoders
4:16 decoder using 2:4 decoders