a. Design 4 to 16 Decoder using 3 to 8 Decoder constructed using 2-4 Decoders.(LOGISIM IMPLEMENTED)

https://docs.google.com/document/d/1akjfecs_P_RaJoGUtcHt7lJr7W42q_knaw-v6Zms6sY/edit?usp=sharing

b. Give the internal circuit of 2 to 4 Decoder using SOP, POS, NAND, NOR logic(loGISIM IMPLEMENTED)

design.

https://docs.google.com/document/d/1akjfecs_P_RaJoGUtcHt7lJr7W42q_knaw-v6Zms6sY/edit?usp=sharing

c. Implement a Combinational logic circuit obtained from your Registration(F' ON LOGISIM)

number using Decoder.

F(A,B,C,D)=Σ(0,2,8,12)

F’(A,B,C,D)=Σ(1,3,4,5,6,8,9,10,11,13,14,15,)

d. Implement Code Convertor Combinational circuit using Decoder.(84-2-1 TO 8421)