CAT 1 Q1
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Author: adel ahammed

Project access type: Public


Derive the Truth table for a three-bit parity generator with inputs A, B, C and Y as output. Implement the circuit for the truth table using 8:1 Multiplexer designed with two input NAND gates with A as input line and select variable as B and C.

Construct four-bit parity checker with inputs A, B, C, D and Y as output using an odd Parity bit, Implement the circuits using 8:1 Multiplexer constructed from 4:1 Multiplexer using D as input line and select variable as A, B and C.

Created: 12 days ago

Updated: 11 days ago

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