Akshita Jain
Member since: 3 years
Educational Institution: vit vellore
Country: India
3.1 (4x4 memory cell design)
3.1 (4x4 memory cell design)
Public
lab fat 20BBS0127
lab fat 20BBS0127
Public
Raushan Kumar
Raushan Kumar
Public
lab fat 20BBS0127
lab fat 20BBS0127
Public
binary cell
binary cell
Public
RAM design
RAM design
Public
2X2 Memory cell design
2X2 Memory cell design
Public
4X4 Memory cell design using 2X2
4X4 Memory cell design using 2X2
Public
4bit Serial Multiplication
4bit Serial Multiplication
Public
3.2 MEMORY DESIGN
3.2 MEMORY DESIGN
Public
4 BIT + SIGN MULTIPLICATER
4 BIT + SIGN MULTIPLICATER
Public
LAB CAT MRGG BATCH
LAB CAT MRGG BATCH
Public
4 BIT SERIES MULTIPLICATION
4 BIT SERIES MULTIPLICATION
Public
CAO LAB DA2
CAO LAB DA2
Public
LAB CATSET C
LAB CATSET C
Public
CAOLABCAT
CAOLABCAT
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LAB CAO SET C
LAB CAO SET C
Public
CAOLABCAT
CAOLABCAT
Public
lab fat mrgg slot
lab fat mrgg slot
Public
CAO LAB DA2
CAO LAB DA2
Public
Untitled
Untitled
Public
4 bit + sign bit(sign and magnitude) multiplication
4 bit + sign bit(sign and magnitude) multiplication
Public
4-Bit Binary Multiplier
4-Bit Binary Multiplier
Public
4-Bit Binary Multiplier
4-Bit Binary Multiplier
Public
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