project.name

bharath mahesh

Member since: 3 years

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CAT1Q5

CAT1Q5
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CAT 1 Q4

CAT 1 Q4
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HW 4

HW 4
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HW3

HW3
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HW4

HW4
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HW 4

HW 4
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CAT 1 Q4

CAT 1 Q4
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COUNTERS

COUNTERS
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CAT1Q7

CAT1Q7
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CAT1Q8

CAT1Q8
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CAT 2 Q3

CAT 2 Q3
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CAT 2 Q4

CAT 2 Q4
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CAT 2 Q2

CAT 2 Q2
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CAT 2 Q8

CAT 2 Q8
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CAT 2 Q9

CAT 2 Q9
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CAT 2 Q9

CAT 2 Q9
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CAT 1 Q4

CAT 1 Q4
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LAB FAT

LAB FAT
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CAT 2 Q8

CAT 2 Q8
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TASK 4

TASK 4
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decoder and mux 2'complement

decoder and mux 2'complement
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DA1dld

DA1dld
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DA!

DA!
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DA2

DA2
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CAT2 Q7

CAT2 Q7
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HW6-GIVEN

HW6-GIVEN
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HW5

HW5
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CAT 2 Q5 DECODER CIRCUIT

CAT 2 Q5 DECODER CIRCUIT
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TASK 3

TASK 3
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CAT 2 Q4

CAT 2 Q4
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g

g
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HW 1 and HW2

HW 1 and HW2
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HW6

HW6
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CAT 2 Q5 - 4:16 Decoder using NOR logic.

CAT 2 Q5 - 4:16 Decoder using NOR logic.
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DA1

DA1
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CAT 2 Q5 - 4:16 Decoder using NOR logic.

CAT 2 Q5 - 4:16 Decoder using NOR logic.
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