DA2

gopi hw4

TASK2 USING DECODER

4-Bit Synchronous Up Counter

NAME AND REG NO. USING 7 SEGMENT DECODER

CAT: design the internal structure of Circuit given using NAND gates.

VIVA_4-1

TASK 1 POS using 4:16 decoder

8:1 MUX FOR TASK-2

task1 using 4:16 decoder

6) 1X16 DEMULTIPLEXER FOR C

TTG

NAME REG.NO

Aditya HW-4

GOPI VIVA 3

GOPI VIVA 1

ADITYA VIVA 2

TASK 4 CIRCUITS

TASK 3 CIRCUITS

4 ->1 multiplexer using 2->1 Multiplexers

aryan khare task 4

varun task3

4 ->1 multiplexer using 2->1 Multiplexers

CAT: implement the equation using decoder

CAT: IMPLEMENT USING NOR LOGIC

CAT 2

VARUN PANDEY DUAL MUX

Ranadheer task3 links

LABFAT 2OMIC0085

task3

3 input OR gate using 4:1 MUX

Untitled

4-bit binary synchronous counter using JK flip flop

BCD to excess 3 code using 1:8 DEMUX

CAT. : IMPLELEMENT FROM DECODER

3 INPUT OR gate using 1:4 Demux

viva 3

IMPLEMENTATION OF CIRCUIT USING MULTIPLEXER

CAT.: DUAL MUX

8:1 IMPLEMENTATION

CIRCUIT DESIGN USING MUX

Untitled

NAME

ADITYA VIVA 1

SISO Shift register using D FF

3 INPUT OR gate using 1:4 Demux

ADITYA VIVA 3

8:1 MUX using 4:1 MUX & 2:1 MUX

1:4 DEMUX

CAT: USING DECODER , DESIGN THE CLC

4 bit synchronous down counter using jk flip flop

MID IMPLEMENTATION OF CIRCUIT USING MULTIPLEXER

TASK 5 CIRCUITS

4-bit right shift register

aryan khare task 4

4 BIT Binary Ripple counter using D FF

16:1 MUX USING 8:1 MUX

7 input NOR GATE

BCD TO GREY USING MUX

Design 1 bit comparator using 4:1 MUX

2 bit increment /decrement circuit

3 input OR gate using 4:1 MUX

3 input OR gate using 4:1 MUX