project.name

Manish Kumar Sharma

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

DA2

DA2
Public
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gopi hw4

gopi hw4
Public
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TASK2 USING DECODER

TASK2 USING DECODER
Public
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NAME AND REG NO. USING 7 SEGMENT DECODER

NAME AND REG NO. USING 7 SEGMENT DECODER
Public
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CAT: design the internal structure of Circuit given using NAND gates.

CAT: design the internal structure of Circuit given using NAND gates.
Public
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VIVA_4-1

VIVA_4-1
Public
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TASK 1 POS using 4:16 decoder

TASK 1 POS using 4:16 decoder
Public
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7 input NOR GATE

7 input NOR GATE
Public
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BCD TO GREY USING MUX

BCD TO GREY USING MUX
Public
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8:1 MUX FOR TASK-2

8:1 MUX FOR TASK-2
Public
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3 input OR gate using 4:1 MUX

3 input OR gate using 4:1 MUX
Public
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task1 using 4:16 decoder

task1 using 4:16 decoder
Public
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6) 1X16 DEMULTIPLEXER FOR C

6) 1X16 DEMULTIPLEXER FOR C
Public
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TTG

TTG
Public
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NAME REG.NO

NAME REG.NO
Public
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Aditya HW-4

Aditya HW-4
Public
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GOPI VIVA 3

GOPI VIVA 3
Public
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GOPI VIVA 1

GOPI VIVA 1
Public
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ADITYA VIVA 2

ADITYA VIVA 2
Public
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TASK 4 CIRCUITS

TASK 4 CIRCUITS
Public
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TASK 3 CIRCUITS

TASK 3 CIRCUITS
Public
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4 ->1 multiplexer using 2->1 Multiplexers

4 ->1 multiplexer using 2->1 Multiplexers
Public
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aryan khare task 4

aryan khare task 4
Public
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varun task3

varun task3
Public
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4 ->1 multiplexer using 2->1 Multiplexers

4 ->1 multiplexer using 2->1 Multiplexers
Public
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CAT: implement the equation using decoder

CAT: implement the equation using decoder
Public
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CAT: IMPLEMENT USING NOR LOGIC

CAT: IMPLEMENT USING NOR LOGIC
Public
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CAT 2

CAT 2
Public
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VARUN PANDEY DUAL MUX

VARUN PANDEY DUAL MUX
Public
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Ranadheer task3 links

Ranadheer task3 links
Public
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LABFAT 2OMIC0085

LABFAT 2OMIC0085
Public
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task3

task3
Public
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3 input OR gate using 4:1 MUX

3 input OR gate using 4:1 MUX
Public
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Untitled

Untitled
Public
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4-bit binary synchronous counter using JK flip flop

4-bit binary synchronous counter using JK flip flop
Public
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BCD to excess 3 code using 1:8 DEMUX

BCD to excess 3 code using 1:8 DEMUX
Public
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2 bit increment /decrement circuit

2 bit increment /decrement circuit
Public
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CAT. : IMPLELEMENT FROM DECODER

CAT. : IMPLELEMENT FROM DECODER
Public
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3 INPUT OR gate using 1:4 Demux

3 INPUT OR gate using 1:4 Demux
Public
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viva 3

viva 3
Public
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IMPLEMENTATION OF CIRCUIT USING MULTIPLEXER

IMPLEMENTATION OF CIRCUIT USING MULTIPLEXER
Public
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CAT.: DUAL MUX

CAT.: DUAL MUX
Public
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8:1 IMPLEMENTATION

8:1 IMPLEMENTATION
Public
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CIRCUIT DESIGN USING MUX

CIRCUIT DESIGN USING MUX
Public
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Untitled

Untitled
Public
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NAME

NAME
Public
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ADITYA VIVA 1

ADITYA VIVA 1
Public
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SISO Shift register using D FF

SISO Shift register using D FF
Public
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3 INPUT OR gate using 1:4 Demux

3 INPUT OR gate using 1:4 Demux
Public
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ADITYA VIVA 3

ADITYA VIVA 3
Public
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8:1 MUX using 4:1 MUX & 2:1 MUX

8:1 MUX using 4:1 MUX & 2:1 MUX
Public
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1:4 DEMUX

1:4 DEMUX
Public
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CAT: USING DECODER , DESIGN THE CLC

CAT: USING DECODER , DESIGN THE CLC
Public
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4 bit synchronous down counter using jk flip flop

4 bit synchronous down counter using jk flip flop
Public
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MID IMPLEMENTATION OF CIRCUIT USING MULTIPLEXER

MID IMPLEMENTATION OF CIRCUIT USING MULTIPLEXER
Public
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TASK 5 CIRCUITS

TASK 5 CIRCUITS
Public
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4-bit right shift register

4-bit right shift register
Public
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aryan khare task 4

aryan khare task 4
Public
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Design 1 bit comparator using 4:1 MUX

Design 1 bit comparator using 4:1 MUX
Public
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4 BIT Binary Ripple counter using D FF

4 BIT Binary Ripple counter using D FF
Public
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16:1 MUX USING 8:1 MUX

16:1 MUX USING 8:1 MUX
Public
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4-Bit Synchronous Up Counter

4-Bit Synchronous Up Counter
Public
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3 input OR gate using 4:1 MUX

3 input OR gate using 4:1 MUX
Public
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No result image
Manish Kumar Sharma is not a collaborator of any project.