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DA2
DA2gopi hw4
gopi hw4TASK2 USING DECODER
TASK2 USING DECODERNAME AND REG NO. USING 7 SEGMENT DECODER
NAME AND REG NO. USING 7 SEGMENT DECODERCAT: design the internal structure of Circuit given using NAND gates.
CAT: design the internal structure of Circuit given using NAND gates.VIVA_4-1
VIVA_4-1TASK 1 POS using 4:16 decoder
TASK 1 POS using 4:16 decoder8:1 MUX FOR TASK-2
8:1 MUX FOR TASK-2task1 using 4:16 decoder
task1 using 4:16 decoder6) 1X16 DEMULTIPLEXER FOR C
6) 1X16 DEMULTIPLEXER FOR CTTG
TTGNAME REG.NO
NAME REG.NOAditya HW-4
Aditya HW-4GOPI VIVA 3
GOPI VIVA 3GOPI VIVA 1
GOPI VIVA 1ADITYA VIVA 2
ADITYA VIVA 2TASK 4 CIRCUITS
TASK 4 CIRCUITSTASK 3 CIRCUITS
TASK 3 CIRCUITS4 ->1 multiplexer using 2->1 Multiplexers
4 ->1 multiplexer using 2->1 Multiplexersaryan khare task 4
aryan khare task 4varun task3
varun task34 ->1 multiplexer using 2->1 Multiplexers
4 ->1 multiplexer using 2->1 MultiplexersCAT: implement the equation using decoder
CAT: implement the equation using decoderCAT: IMPLEMENT USING NOR LOGIC
CAT: IMPLEMENT USING NOR LOGICCAT 2
CAT 2VARUN PANDEY DUAL MUX
VARUN PANDEY DUAL MUXRanadheer task3 links
Ranadheer task3 linksLABFAT 2OMIC0085
LABFAT 2OMIC0085task3
task33 input OR gate using 4:1 MUX
3 input OR gate using 4:1 MUXUntitled
Untitled4-bit binary synchronous counter using JK flip flop
4-bit binary synchronous counter using JK flip flopBCD to excess 3 code using 1:8 DEMUX
BCD to excess 3 code using 1:8 DEMUXCAT. : IMPLELEMENT FROM DECODER
CAT. : IMPLELEMENT FROM DECODER3 INPUT OR gate using 1:4 Demux
3 INPUT OR gate using 1:4 Demuxviva 3
viva 3IMPLEMENTATION OF CIRCUIT USING MULTIPLEXER
IMPLEMENTATION OF CIRCUIT USING MULTIPLEXERCAT.: DUAL MUX
CAT.: DUAL MUX8:1 IMPLEMENTATION
8:1 IMPLEMENTATIONCIRCUIT DESIGN USING MUX
CIRCUIT DESIGN USING MUXUntitled
UntitledNAME
NAMEADITYA VIVA 1
ADITYA VIVA 1SISO Shift register using D FF
SISO Shift register using D FF3 INPUT OR gate using 1:4 Demux
3 INPUT OR gate using 1:4 DemuxADITYA VIVA 3
ADITYA VIVA 38:1 MUX using 4:1 MUX & 2:1 MUX
8:1 MUX using 4:1 MUX & 2:1 MUX1:4 DEMUX
1:4 DEMUXCAT: USING DECODER , DESIGN THE CLC
CAT: USING DECODER , DESIGN THE CLC4 bit synchronous down counter using jk flip flop
4 bit synchronous down counter using jk flip flopMID IMPLEMENTATION OF CIRCUIT USING MULTIPLEXER
MID IMPLEMENTATION OF CIRCUIT USING MULTIPLEXERTASK 5 CIRCUITS
TASK 5 CIRCUITS4-bit right shift register
4-bit right shift registeraryan khare task 4
aryan khare task 44-Bit Synchronous Up Counter
4-Bit Synchronous Up Counter4 BIT Binary Ripple counter using D FF
4 BIT Binary Ripple counter using D FF16:1 MUX USING 8:1 MUX
16:1 MUX USING 8:1 MUX7 input NOR GATE
7 input NOR GATEBCD TO GREY USING MUX
BCD TO GREY USING MUXDesign 1 bit comparator using 4:1 MUX
Design 1 bit comparator using 4:1 MUX2 bit increment /decrement circuit
2 bit increment /decrement circuit3 input OR gate using 4:1 MUX
3 input OR gate using 4:1 MUX3 input OR gate using 4:1 MUX
3 input OR gate using 4:1 MUX