project.name

AKILESH S CSEUG-2020

Member since: 3 years

Educational Institution: "Kalasalingam Academy of Research and Education"

Country: India

logic gates

logic gates
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Parity

Parity
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Code Conventers

Code Conventers
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Logic Gates

Logic Gates
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De Morgan Law

De Morgan Law
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Disrtributed Law

Disrtributed Law
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K-Map

K-Map
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mux

mux
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DMUX

DMUX
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Sequential logic circuit

Sequential logic circuit
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Half Adder

Half Adder
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Full Adder

Full Adder
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Half Subtractor

Half Subtractor
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Full Subtractor

Full Subtractor
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Encoder

Encoder
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Decoder

Decoder
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ADDERS

ADDERS
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Shift Registers

Shift Registers
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Counters

Counters
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Magnitude Comparator

Magnitude Comparator
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Seven Seg Display

Seven Seg Display
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Decoder (Model lab)

Decoder (Model lab)
Public
project.name
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AKILESH S CSEUG-2020 is not a collaborator of any project.