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BT19ECE045_Jayant Rahate

Member since: 713 days

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Experiment 2: Verification of De Morgan's Law

Experiment 2: Verification of De Morgan's Law
Public
Experiment 2: Verification of De Morgan's Law

Experiment 9:To design and implement a logic circuit for full subtractor using NAND gates

Experiment 9:To design and implement a logic circuit for full subtractor using NAND gates
Public
Experiment 9:To design and implement a logic circuit for full subtractor using NAND gates

Experiment 7:To verify the truth tables of 3 bit Decoder

Experiment 7:To verify the truth tables of 3 bit Decoder
Public
Experiment 7:To verify the truth tables of 3 bit Decoder

Implement the Boolean function using minimum number of NAND Gates

Implement the Boolean function using minimum number of NAND Gates
Public
Implement the Boolean function using minimum number of NAND Gates

Experiment 6: To verify the truth tables of 8x1 multiplexer

Experiment 6: To verify the truth tables of 8x1 multiplexer
Public
Experiment 6: To verify the truth tables of 8x1 multiplexer

Implement the Boolean function using minimum number of NAND Gates

Implement the Boolean function using minimum number of NAND Gates
Public
Implement the Boolean function using minimum number of NAND Gates

Experiment 12: Verification of truth table of four bit bidirectional shift register

Experiment 12: Verification of truth table of four bit bidirectional shift register
Public
Experiment 12: Verification of truth table of four bit bidirectional shift register

Experiment 1:Verifying truth table for gates

Experiment 1:Verifying truth table for gates
Public
Experiment 1:Verifying truth table for gates

Experiment 11:To convert JK to T Flip flop, JK to D Flip flop

Experiment 11:To convert JK to T Flip flop, JK to D Flip flop
Public
Experiment 11:To convert JK to T Flip flop, JK to D Flip flop

Experiment 8: To design and implement a logic circuit for full adder using NAND gates

Experiment 8: To design and implement a logic circuit for full adder using NAND gates
Public
Experiment 8:  To design and implement a logic circuit for full adder using NAND gates

Experiment 3:To implement the following boolean functions using minimum number of NAND Gates

Experiment 3:To implement the following boolean functions using minimum number of NAND Gates
Public
Experiment 3:To implement the following boolean functions using minimum number of NAND Gates

Experiment 10: J-K Flip Flop (VERIFICATION AND IMPLEMENTATION OF MASTER SLAVE USING J-K FLIP FLOP)

Experiment 10: J-K Flip Flop (VERIFICATION AND IMPLEMENTATION OF MASTER SLAVE USING J-K FLIP FLOP)
Public
Experiment 10: J-K Flip Flop (VERIFICATION AND IMPLEMENTATION OF MASTER SLAVE USING J-K FLIP FLOP)

Experiment 11: Implementation of T Flip Flop and D Flip Flop using J-K Flip Flop

Experiment 11: Implementation of T Flip Flop and D Flip Flop using J-K Flip Flop
Public
Experiment 11: Implementation of T Flip Flop and D Flip Flop using J-K Flip Flop

Experiment 5: To design and verify THREE input majority gates

Experiment 5: To design and verify THREE input majority gates
Public
Experiment 5: To design and verify THREE input majority gates
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