project.name

BT19ECE013_Sahiesh Bakliwal

Member since: 3 years

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experiment 8

experiment 8
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full adder

full adder
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Master Slave Flip Flop using J-K FlipFlop

Master Slave Flip Flop using J-K FlipFlop
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full subtractor

full subtractor
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four bit bidirectional shift register

four bit bidirectional shift register
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T flip flop

T flip flop
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BT19ECE013 Sahiesh Bakliwal MUX 8:1

BT19ECE013 Sahiesh Bakliwal MUX 8:1
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conversion of JK flip flop to T and D flip flop

conversion of JK flip flop to T and D flip flop
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BT19ECE013 Sahiesh Bakliwal

BT19ECE013 Sahiesh Bakliwal
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BT19ECE013 Sahiesh Bakliwal DeMorgan's Law

BT19ECE013 Sahiesh Bakliwal DeMorgan's Law
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BT19ECE013 Sahiesh Bakliwal Boolean Equation

BT19ECE013 Sahiesh Bakliwal Boolean Equation
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BT19ECE013 Sahiesh Bakliwal - Three Input Majority Gate

BT19ECE013 Sahiesh Bakliwal - Three Input Majority Gate
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BT19ECE013 Sahiesh Bakliwal NAND

BT19ECE013 Sahiesh Bakliwal NAND
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BT19ECE013_Sahiesh Bakliwal is not a collaborator of any project.

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