project.name

Ajaypal Singh Mahal

Member since: 3 years

Educational Institution: GURU NANAK DEV ENGINEERING COLLEGE ,LUDHIANA

Country: India

ajaypal project 11 xor gate 2

ajaypal project 11 xor gate 2
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ajaypal project 2

ajaypal project 2
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ajaypal project 7

ajaypal project 7
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nand gate practical 8

nand gate practical 8
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ajaypal project xnor 3.0

ajaypal project xnor 3.0
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ajaypal xnor gate 2nd method

ajaypal xnor gate 2nd method
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ajaypal project 9 nor table

ajaypal project 9 nor table
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ajaypal project 10

ajaypal project 10
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ajaypal project 1

ajaypal project 1
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ajaypal project 3

ajaypal project 3
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ajaypal project 5

ajaypal project 5
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ajaypal project 4

ajaypal project 4
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ajaypal projetct 6

ajaypal projetct 6
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ajaypal Half adder project new

ajaypal Half adder project new
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LOGICALLY HALF SUBTRACTOR

LOGICALLY HALF SUBTRACTOR
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LOGICALLY FULL ADDER SUBTRACTOR

LOGICALLY FULL ADDER SUBTRACTOR
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Logically synchronous up counter

Logically synchronous up counter
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Logically synchronous up counter NEW .1

Logically synchronous up counter NEW .1
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logically SYNCHRONOUS DOWN COUNTER

logically SYNCHRONOUS DOWN COUNTER
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Logiclly full adder cicuit diagram

Logiclly full adder cicuit diagram
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Logically decoder circuit diagram

Logically decoder circuit diagram
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3 TO 8 DECODER

3 TO 8 DECODER
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ENCODER

ENCODER
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3 to 8 encoder

3 to 8 encoder
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multiplexer diagram new

multiplexer diagram new
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LOGICALLY DEMULTIPLEXER DIAGRAM

LOGICALLY DEMULTIPLEXER DIAGRAM
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sr flip flop using nor gate

sr flip flop using nor gate
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Sr flip flop using nand gate

Sr flip flop using nand gate
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master jk flip flop

master jk flip flop
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logically 4*1 multiplexer

logically 4*1 multiplexer
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Logically d flip flop circuit

Logically d flip flop circuit
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Logically t flip flop circuit

Logically t flip flop circuit
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Logically d flip flop using nand gates

Logically d flip flop using nand gates
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Logically asynchronous up counter

Logically asynchronous up counter
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Logically Asychronous Down counter

Logically Asychronous Down counter
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ajaypal project 4

ajaypal project 4
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LOGICALLY DECODER 4 BIT SYNCHRONOUS COUNTER

LOGICALLY DECODER 4 BIT SYNCHRONOUS COUNTER
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logically t flip flop using nand gate

logically t flip flop using nand gate
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jk flip flop diagram

jk flip flop diagram
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Ajaypal Singh Mahal is not a collaborator of any project.

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