project.name

ritik varshney

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

Universal Gate

Universal Gate
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3 Bit SISO

3 Bit SISO
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SIPO

SIPO
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Half Substractor

Half Substractor
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Synchronous Counter

Synchronous Counter
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ASSIGNMENT 1

ASSIGNMENT 1
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NAND Gate

NAND Gate
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Full Subtractor

Full Subtractor
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4 Bit SIPO

4 Bit SIPO
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Counter

Counter
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Untitled

Untitled
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Full Adder

Full Adder
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Half Adder

Half Adder
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4 Bit PIPO

4 Bit PIPO
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Mod 4 Synchronous

Mod 4 Synchronous
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4 Bit Adder

4 Bit Adder
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4 Bit SIPO Shify Register

4 Bit SIPO Shify Register
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4 BIT SUB

4 BIT SUB
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7 Segment Display

7 Segment Display
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3 Bit SISO

3 Bit SISO
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Seven Segment

Seven Segment
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JK Flip Flop

JK Flip Flop
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Half Adder using Basic Gates

Half Adder using Basic Gates
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Clocked SR Flip Flop

Clocked SR Flip Flop
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Clocked SR Flip Flop

Clocked SR Flip Flop
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EXPERIMENT NO 1

EXPERIMENT NO 1
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EXPERIMENT NO 3

EXPERIMENT NO 3
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EXPERIMENT NO 2

EXPERIMENT NO 2
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binary adder

binary adder
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half and full sub

half and full sub
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7 segment directly with dont care

7 segment directly with dont care
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T FLIP FLOP

T FLIP FLOP
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JK FLIP FLOP

JK FLIP FLOP
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SR FLIPFLOP

SR FLIPFLOP
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CLOCKED SR FLIP FLOP

CLOCKED SR FLIP FLOP
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D FLIP FLOP

D FLIP FLOP
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swift

swift
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sychronous down counter

sychronous down counter
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asychronous decade counter

asychronous decade counter
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sychronous up counter

sychronous up counter
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aychronous ripple counter

aychronous ripple counter
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alu

alu
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