project.name

Sairam

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

EXP1(2) OR

EXP1(2) OR
Public
project.name

EXP1(4) NAND

EXP1(4) NAND
Public
project.name

EXP1(5) NOR

EXP1(5) NOR
Public
project.name

EXP11(1)

EXP11(1)
Public
project.name

exp1(6) EXOR

exp1(6) EXOR
Public
project.name

EXP2(1(2)) AND

EXP2(1(2)) AND
Public
project.name

EXP2(2(2)) OR

EXP2(2(2)) OR
Public
project.name

EXP5

EXP5
Public
project.name

exp33

exp33
Public
project.name

EXP2(1(1)) NOR

EXP2(1(1)) NOR
Public
project.name

EXP2(2(1)) NAND

EXP2(2(1)) NAND
Public
project.name

EXP1(3) NOT

EXP1(3) NOT
Public
project.name

BF---NAND

BF---NAND
Public
project.name

experiment 7

experiment 7
Public
project.name

EXP1(3) NOT

EXP1(3) NOT
Public
project.name

NOT using NAND gate

NOT using NAND gate
Public
project.name

EXP1(1) AND

EXP1(1) AND
Public
project.name

exp11(2)

exp11(2)
Public
project.name

8:1 MUX

8:1 MUX
Public
project.name

exp11(2)

exp11(2)
Public
project.name

AND using NAND

AND using NAND
Public
project.name

adder using nand

adder using nand
Public
project.name

SUBTRACTOR

SUBTRACTOR
Public
project.name

MASTER SLAVE

MASTER SLAVE
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

JK Flip Flop

JK Flip Flop
Public
project.name

Flip-Flops using NAND Gate

Flip-Flops using NAND Gate
Public
project.name

Master Slave JK Flip-flop

Master Slave JK Flip-flop
Public
project.name

EXOR using NAND

EXOR using NAND
Public
project.name
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