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EXP1(2) OR
EXP1(2) OREXP1(4) NAND
EXP1(4) NANDEXP1(5) NOR
EXP1(5) NOREXP11(1)
EXP11(1)exp1(6) EXOR
exp1(6) EXOREXP2(1(2)) AND
EXP2(1(2)) ANDEXP2(2(2)) OR
EXP2(2(2)) OREXP5
EXP5exp33
exp33EXP2(1(1)) NOR
EXP2(1(1)) NOREXP2(2(1)) NAND
EXP2(2(1)) NANDEXP1(3) NOT
EXP1(3) NOTBF---NAND
BF---NANDexperiment 7
experiment 7EXP1(3) NOT
EXP1(3) NOTNOT using NAND gate
NOT using NAND gateEXP1(1) AND
EXP1(1) ANDexp11(2)
exp11(2)8:1 MUX
8:1 MUXexp11(2)
exp11(2)AND using NAND
AND using NANDadder using nand
adder using nandSUBTRACTOR
SUBTRACTORMASTER SLAVE
MASTER SLAVEUntitled
UntitledUntitled
UntitledJK Flip Flop
JK Flip FlopFlip-Flops using NAND Gate
Flip-Flops using NAND GateMaster Slave JK Flip-flop
Master Slave JK Flip-flopEXOR using NAND
EXOR using NAND