No_name
Member since: 4 years
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FAMILIARISATION OF LOGIC GATES WITH UNIVERSAL GATES
FAMILIARISATION OF LOGIC GATES WITH UNIVERSAL GATES
Public
ALU 4-Bit
ALU 4-Bit
Public
4 bit
4 bit
Public
16 BIT ALU
16 BIT ALU
Public
kk
kk
Public
Untitled
Untitled
Public
16 BIT ALU
16 BIT ALU
Public
Untitled
Untitled
Public
3.2 MEMORY DESIGN
3.2 MEMORY DESIGN
Public
DA 3
DA 3
Public
DA 3.2
DA 3.2
Public
Lab CAT
Lab CAT
Public
Lab CAT
Lab CAT
Public
Lab CAT
Lab CAT
Public
Lab CAT
Lab CAT
Public
Lab CAT
Lab CAT
Public
LAB CAT MRGG BATCH
LAB CAT MRGG BATCH
Public
RAM ROM
RAM ROM
Public
PR
PR
Public
PR
PR
Public
PR
PR
Public
PR
PR
Public
PR
PR
Public
asd
asd
Public
asd
asd
Public
asd
asd
Public
asd
asd
Public
PR
PR
Public
PR
PR
Public
assignment 2
assignment 2
Public
assignment 2
assignment 2
Public
a
a
Public
4x4 memory cell design
4x4 memory cell design
Public
4x4 memory cell design
4x4 memory cell design
Public
3.2 MEMORY DESIGN PROBLEM 01
3.2 MEMORY DESIGN PROBLEM 01
Public
4 Bit ALU
4 Bit ALU
Public
4 Bit ALU
4 Bit ALU
Public
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