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FULL LADDER
FULL LADDERDE-multiplexer
DE-multiplexerassignment 1 question 3
assignment 1 question 3COUNTER-3 BIT UP AND DOWN COUNTER
COUNTER-3 BIT UP AND DOWN COUNTERCOUNTER-3 BIT SYN DOWN COUNTER
COUNTER-3 BIT SYN DOWN COUNTERCOUNTER-3 BIT SYN DOWN COUNTER
COUNTER-3 BIT SYN DOWN COUNTERSISO
SISOSIPO
SIPOCOUNTER- RIPPLE 4 BIT UP/DOWN COUNTER
COUNTER- RIPPLE 4 BIT UP/DOWN COUNTEREXPER-2, QNO-2
EXPER-2, QNO-2CONFORMATION OF LOGIC GATES AND TRUTH TABLE
CONFORMATION OF LOGIC GATES AND TRUTH TABLEBINARY TO GARY
BINARY TO GARYENCODER
ENCODERHALF LADDER
HALF LADDERBOOLEAN EXPRESSION
BOOLEAN EXPRESSIONHALF ADDER
HALF ADDERFULL LADDER
FULL LADDERMULTIPLEXER
MULTIPLEXERd to jk flip flop
d to jk flip flopSR,JK,D,T FLIPFLOP
SR,JK,D,T FLIPFLOPBDL TO GRAY
BDL TO GRAYEXPER-2QNO:1
EXPER-2QNO:1assignment question 1
assignment question 1assiginment 1 question 4
assiginment 1 question 4COUNTER-MODE-5 COUNTER
COUNTER-MODE-5 COUNTERCOUNTER - 4 BIT SYN DOWN COUNTER
COUNTER - 4 BIT SYN DOWN COUNTERPISO
PISOCOUNTER-4 BIT RIPPLE UP COUNTER
COUNTER-4 BIT RIPPLE UP COUNTERCOUNTERS-3BIT RIPPLE DOWN COUNTER
COUNTERS-3BIT RIPPLE DOWN COUNTER3 BIT SYNCHRONOUS UP COUNTER
3 BIT SYNCHRONOUS UP COUNTERUPE
UPEEX-6 parallel in series out shift registers
EX-6 parallel in series out shift registersPIPO
PIPOUNIVERSITY PRACTICAL EXAM
UNIVERSITY PRACTICAL EXAMimpement 4:1 mux m(0,1,2,4,6,9,12,14) impement 4:1 mux m(0,1,2,4,6,9,12,14)
impement 4:1 mux m(0,1,2,4,6,9,12,14) impement 4:1 mux m(0,1,2,4,6,9,12,14)MAGNITUDE CODE
MAGNITUDE CODEassignment 1 question 2
assignment 1 question 2DECODER
DECODER