project.name

SIDDHIKA SINGH

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

Full Adder

Full Adder
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Demultiplexer(DEMUX)

Demultiplexer(DEMUX)
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AND gate

AND gate
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OR gate

OR gate
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OR gate

OR gate
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NOT gate

NOT gate
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AND gate

AND gate
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OR gate

OR gate
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NAND gate

NAND gate
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XNOR gate

XNOR gate
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NOR gate

NOR gate
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XOR gate

XOR gate
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NAND gate as OR gate

NAND gate as OR gate
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NAND gate as NOT gate

NAND gate as NOT gate
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NOR gate as OR gate

NOR gate as OR gate
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NOR gate as AND gate

NOR gate as AND gate
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NOR gate as NOT gate

NOR gate as NOT gate
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NAND gate as AND gate

NAND gate as AND gate
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full adder

full adder
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full adder

full adder
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full adder

full adder
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Half Adder

Half Adder
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half adder

half adder
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Half Subtractor

Half Subtractor
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Full adder

Full adder
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Untitled

Untitled
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Multiplexer(MUX)

Multiplexer(MUX)
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half adder

half adder
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ENCODER

ENCODER
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DECODER

DECODER
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SIDDHIKA SINGH is not a collaborator of any project.

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