Member since: 3 years
Educational Institution: Victoria University of Wellington
Country: New Zealand
Half Adder
Half AdderD FF Variations
D FF VariationsDe Morgan's Law Proof
De Morgan's Law ProofMultiplexer NAND Gate Proof
Multiplexer NAND Gate ProofHalf Adder
Half Adder4-Bit Counters (using JK FFs)
4-Bit Counters (using JK FFs)NAND Gate
NAND GateHalf Adder using NAND, NOR, and NOT
Half Adder using NAND, NOR, and NOTBasic SC Latch with Enable
Basic SC Latch with EnableBasic SC Latch
Basic SC LatchUntitled
UntitledTemperature Monitor Latch
Temperature Monitor Latch3-Bit Prime Number Detector using Dual 4:1 MUX
3-Bit Prime Number Detector using Dual 4:1 MUX3-Bit Prime Number Detector
3-Bit Prime Number Detector