SR Flipflop and D Flipflop(by using SR Flipflop)

Demorgans

exnor and eor Paula Cuervo

Electronics Logic_Lab_Full_Adder

final exam circuit

16X 1

2

I do my best

1

1 bit su

ring & johnson counter

Lecture_23_Encoders_3_Period

10A_Quiz_3_IT_3_Period

NAND & Kmap

flip flop NAnd

flip flop using nand sr

flip flop nor gate

lecture 24

part 2 y 3

nand

Lecture_25_FlipFlops_4_Period

3 bit siso shift

3 BIT SIPO SHIFT REGISTER

3 bit piso

3 bit pipo shift

example3

3.2

3.1

even parity

odd parity

gray code

kMAP

KMAP 2

4 bit binary subtractor

Lecture_26_Shift_Register_4_Period

F(A,B,C) = A'BC+BC'+AB

quiz electronic 3

J

Lecture_21_Binary Subtractor_3_Period

2-4 DECODER

3-8

3 BIT SIPO SHIFT REGISTER

5 BIT SIPO SHIFT REGISTER

Master-Slave D-Flipflop

4 bit counter

Asynchronous Binary Up Counter

Synchronous Binary Down Counter

Asynchronous Binary Up Counter

Asynchronous Binary Up 5 bit

Synchronous Binary Down 5 bit