Synchronous Binary Up Counter

SISO

3.2

4-bit Binary Adder / Subtractor

Q= (A.B.C)+A.(B'+C')

5-Bit SIPO

16x1 Multiplexer

Exam

Ring Counter

4x1 Multiplexer

NAND gates Realization

3.1

3.6

3.5

Gray code converte

Gray code converte x2

Odd parity with 3 & 4 bits input X2

4 to 2 Encoder

Asynchronous Binary Up Counter

Logical_Circuit

EXOR, EXNOR

PIPO

Odd parity with 3 & 4 bits input

EXOR, EXNOR gate

4-bit Binary Subtractor

Table

Desarrrollo BIM 3ER PERIODO 2B

QUIZ 3 IT

J-K Master/Slave Flip-Flop:

8x1 Multiplexer

D Edge-Triggered Flip-Flop

PISO

S-R FIip-Flop:

1- (A.B)' =A' + B' 2- (A+B)' = A'. B'

Q2 electronica 13-08-2021

K-map 1 & 2

4 to 16 Decoder

3

Johnson Ring Counter

Even parity with 3 & 4 bits input

Asynchronous Binary Down Counter

Priority Encoder

SIPO

Bim 3er periodo A

POS 3&4

Clocked enabled SR and D Flipflop

3 to 8 Decoder

2 to 4 Decoder

Q= (A.B.C)+A.(B'+C')

half_adder

Full Adder logic circuit

Parity Checker

Half Adder

Master-Slave D-Flipflop circuit

Synchronous Binary Down Counter

Even parity with 3 & 4 bits input x2

4 Bit Adder Block Diagram

3.4

Octal to Binary Encoder