Member since: 3 years
Educational Institution: Jahangirnagar University
Country: Bangladesh
Lab 07- MUX (4:1 Multiplexer, 8:1 Multiplexer)
Lab 07- MUX (4:1 Multiplexer, 8:1 Multiplexer)Lab 04- Implementation of Half Adder and Design a Full Adder using Half Adder
Lab 04- Implementation of Half Adder and Design a Full Adder using Half AdderLab 02- Introduction to Logic Gates and its Verification with Truth Table
Lab 02- Introduction to Logic Gates and its Verification with Truth TableLab 05- Designing and Implementing 1 bit and 2 bit Comparator
Lab 05- Designing and Implementing 1 bit and 2 bit ComparatorLab 06- Decimal to BCD
Lab 06- Decimal to BCDLab 03- Implementation of the given Boolean function using logic gates in both SOP and POS
Lab 03- Implementation of the given Boolean function using logic gates in both SOP and POS