project.name

Kavitha R Computer Science

Member since: 5 years

Educational Institution: Not Entered

Country: Not Entered

Syn-Counter

Syn-Counter
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trail

trail
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AND

AND
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kavi

kavi
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Untitled

Untitled
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Shift Registers

Shift Registers
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Latch Vs Flip-Flop

Latch Vs Flip-Flop
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Demo

Demo
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1234_Q4

1234_Q4
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Shift Registers

Shift Registers
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Logical gates

Logical gates
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Counters

Counters
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SIMULATION

SIMULATION
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BCD-7Seg

BCD-7Seg
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Latch Vs Flip-Flop

Latch Vs Flip-Flop
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J K FlipFlop

J K FlipFlop
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ENCODERS AND DECODERS

ENCODERS AND DECODERS
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Parallel Adder

Parallel Adder
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MOD Counter

MOD Counter
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RS Flipflop

RS Flipflop
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RS latch

RS latch
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Logical gates

Logical gates
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kavi

kavi
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kavi1

kavi1
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Test

Test
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XOR

XOR
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D Flip Flop

D Flip Flop
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Ripple UpCounter

Ripple UpCounter
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test2

test2
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2047024_xor_using_nand

2047024_xor_using_nand
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CIA_2047022

CIA_2047022
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2047004

2047004
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2047006

2047006
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2041063_ESETest3

2041063_ESETest3
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Dipta Roy-2047003

Dipta Roy-2047003
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2047003_Component 2

2047003_Component 2
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2047022_CIA_5

2047022_CIA_5
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CIA_5_2047020-MOD 20

CIA_5_2047020-MOD 20
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2047014_CIA-Component 5

2047014_CIA-Component 5
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priyangka_2047005_cia5_comp_final

priyangka_2047005_cia5_comp_final
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Registers

Registers
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Shift Registers

Shift Registers
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Q9

Q9
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DCF CIA 2

DCF CIA 2
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