DESHA JAYA SAI MANJUNATH-CSEUG-2020 BATCH - Circuits

DESHA JAYA SAI MANJUNATH-CSEUG-2020 BATCH

Member since: 3 years

Educational Institution: kalasalingam academy of research an education

Country: India

BASIC LOGIC GATES

BASIC LOGIC GATES

Public

project.name

Shift Register(Sin and Pout)

Shift Register(Sin and Pout)

Public

project.name

multiplexer

multiplexer

Public

project.name

Encoder

Encoder

Public

project.name

half and full adder

half and full adder

Public

project.name

sample eq1

sample eq1

Public

project.name

sample eq2

sample eq2

Public

project.name

DEMUX

DEMUX

Public

project.name

Half and Full Subtractor

Half and Full Subtractor

Public

project.name

Decoder

Decoder

Public

project.name

Asynchronous Counters

Asynchronous Counters

Public

project.name

Comparator

Comparator

Public

project.name

Code Converters

Code Converters

Public

project.name

Flip Flop

Flip Flop

Public

project.name

Full Adder

Full Adder

Public

project.name

Shift registers

Shift registers

Public

project.name

Basic Gates

Basic Gates

Public

project.name

Parity

Parity

Public

project.name

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