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d to jk flip flop
d to jk flip flopEX-6 parallel in parallel ot shift rigisters
EX-6 parallel in parallel ot shift rigistersSR,JK,D,T FLIPFLOP
SR,JK,D,T FLIPFLOPDECODER
DECODERCT-2 ASSINGMENT Q1
CT-2 ASSINGMENT Q1CT2 ASSINGEMENT Q3
CT2 ASSINGEMENT Q3CT2 ASSINGEMENT Q4
CT2 ASSINGEMENT Q4COUNTER- 4 bit ripel up counter
COUNTER- 4 bit ripel up counterCOUNTER - 3 BIT UP AND DOWN COUNTER
COUNTER - 3 BIT UP AND DOWN COUNTEREX-6 parallel in serice out shift registers
EX-6 parallel in serice out shift registersEX-6 - seerial in serial out shift regiters
EX-6 - seerial in serial out shift regitersHALF LADDER
HALF LADDERFULL LADDER
FULL LADDERimpement 4:1 mux m(0,1,2,4,6,9,12,14)
impement 4:1 mux m(0,1,2,4,6,9,12,14)COUNTER -4 BIT SYN DOWN COUMTER
COUNTER -4 BIT SYN DOWN COUMTERHalf Adder
Half AdderEXP-1, QNO:2, GENERATE CIRCUIT BY CHANGING EXPERSION IN TO SOP
EXP-1, QNO:2, GENERATE CIRCUIT BY CHANGING EXPERSION IN TO SOPEXPER-2,QNO:1
EXPER-2,QNO:1BDL TO GRAY
BDL TO GRAYCT-2 ASSSINGMENT 1 Q2
CT-2 ASSSINGMENT 1 Q2ASSIGNMENT I
ASSIGNMENT ICOUNTERS -3 bit ripel down counter
COUNTERS -3 bit ripel down counterCOUNTER - MODE-5 COUNTER
COUNTER - MODE-5 COUNTERCOUNTER - 3 BIT SYN DOWN COUNTER
COUNTER - 3 BIT SYN DOWN COUNTERCOUNTER -rippel 4 bit up/down counter
COUNTER -rippel 4 bit up/down counterEX-6 serial in parallel out shift registers
EX-6 serial in parallel out shift registersDSP PRATICAL EXAM
DSP PRATICAL EXAMmultiplexer
multiplexerEXP-1 conformation of logic gates and truth tabel
EXP-1 conformation of logic gates and truth tabelEXPER-2, QNO-2
EXPER-2, QNO-2Boolean expresion
Boolean expresionFULL LADDER
FULL LADDERDE-multiplexer
DE-multiplexerencoder
encoder