project.name

Michael Jesai

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

Multiplexer

Multiplexer
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4 bit ripple down counter

4 bit ripple down counter
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DFLIPFLOP

DFLIPFLOP
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siso

siso
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piso

piso
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3 bit down ripple counter

3 bit down ripple counter
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4 bit ripple down counter

4 bit ripple down counter
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4 bit synchronous counter using J-K flipflop

4 bit synchronous counter using J-K flipflop
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Half Adder

Half Adder
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logic gates ra1911018010079

logic gates ra1911018010079
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RIPPLE 4 BIT UP DOWN COUNTER

RIPPLE 4 BIT UP DOWN COUNTER
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3 BIT UP DOWN COUNTER

3 BIT UP DOWN COUNTER
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4 BIT SYNCHRONOUS DOWN COUNTER

4 BIT SYNCHRONOUS DOWN COUNTER
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BINARY TO GRAY

BINARY TO GRAY
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ra1911018010079.exp

ra1911018010079.exp
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Binary to ex3

Binary to ex3
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encoder

encoder
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decoder

decoder
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Full adder

Full adder
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Half subtractor

Half subtractor
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full subtractor

full subtractor
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De Multiplexer

De Multiplexer
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TFLIPFLOP

TFLIPFLOP
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JK-FLIPFLOP

JK-FLIPFLOP
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assignment 1

assignment 1
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6exp

6exp
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EXP6

EXP6
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mod5counter

mod5counter
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pipo

pipo
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sipo

sipo
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4 bit ripple up counter

4 bit ripple up counter
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siso

siso
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UNIVERSITY PRACTICAL

UNIVERSITY PRACTICAL
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4 bit async up counter

4 bit async up counter
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ra1911018010079 first expression exp 1

ra1911018010079 first expression exp 1
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MAGNITUDE CODE

MAGNITUDE CODE
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SR-FLIPFLOP

SR-FLIPFLOP
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Michael Jesai is not a collaborator of any project.

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