project.name

Vidhi Kanunga (RA1911018010126)

Member since: 3 years

Educational Institution: Not Entered

Country: India

D and T Flipflop

D and T Flipflop
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Implementation of boolean expressions

Implementation of boolean expressions
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Encoder (4:2)

Encoder (4:2)
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De-multiplexer (1:4)

De-multiplexer (1:4)
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registers

registers
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Full adder and half adder

Full adder and half adder
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Half subtractor and full subtractor

Half subtractor and full subtractor
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Binary to Excess 3

Binary to Excess 3
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SR and JK Flipflop

SR and JK Flipflop
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MULTIPLEXER (4:1)

MULTIPLEXER (4:1)
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DECODER (2:4)

DECODER (2:4)
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3 bit synchronous motor

3 bit synchronous motor
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Untitled

Untitled
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BCD to gray code

BCD to gray code
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Logic Gates Verification

Logic Gates Verification
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MULTIPLEXER (8:1)

MULTIPLEXER (8:1)
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Magnitude Comparator

Magnitude Comparator
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Vidhi Kanunga (RA1911018010126) is not a collaborator of any project.

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