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Binali Abeywickrama

Member since: 3 years

Educational Institution: University of Newcastle Australia

Country: Australia

project A

project A
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ELEC1710 PROJECT A

ELEC1710 PROJECT A
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Q2-D3

Q2-D3
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Untitled

Untitled
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Q2-D0

Q2-D0
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FINAL CIRCUIT

FINAL CIRCUIT
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LAB 1 NOT

LAB 1 NOT
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LAB 1 AND

LAB 1 AND
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LAB 1 NOR

LAB 1 NOR
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LAB 1- OR GATE- USING THREE 2 INPUT NAND GATES

LAB 1- OR GATE- USING THREE 2 INPUT NAND GATES
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LAB 1 -AND GATE- USING TWO 2 INPUT NAND

LAB 1 -AND GATE- USING TWO 2 INPUT NAND
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JK FLIP FLOP COUNTER

JK FLIP FLOP COUNTER
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FINAL CIRCUIT

FINAL CIRCUIT
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FINAL CIRCUIT

FINAL CIRCUIT
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LAB 1 NAND

LAB 1 NAND
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LAB 1 NAND

LAB 1 NAND
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Assignment 2 Full adder

Assignment 2 Full adder
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Q2-D1

Q2-D1
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Q2-D2

Q2-D2
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2 bit asynchronous counter using JK-Flipflop

2 bit asynchronous counter using JK-Flipflop
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2 bit asynchronous counter using JK-Flipflop

2 bit asynchronous counter using JK-Flipflop
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