project.name

Dr Vijay Singh Bist

Member since: 3 years

Educational Institution: Department of Instrumentation Engineering, School of Engineering and Technology, HNB Garhwal University Srinagar (Garhwal)

Country: India

4 X 1 MUX using gates

4 X 1 MUX using gates
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Half adder using MUXs

Half adder using MUXs
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Branch name

Branch name
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Asynchronous MOD-5 Counter

Asynchronous MOD-5 Counter
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4-bit ripple counter

4-bit ripple counter
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Higher MUX using lower MUXs

Higher MUX using lower MUXs
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2-bit synchronous counter

2-bit synchronous counter
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PARITY CHECKER

PARITY CHECKER
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Full Adder From 2 half Adders

Full Adder From 2 half Adders
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Full Adder From 2 half Adders

Full Adder From 2 half Adders
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4 X 1 MUX using gates

4 X 1 MUX using gates
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4-bit ripple counter

4-bit ripple counter
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SR flip- flop using NAND

SR flip- flop using NAND
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Design basic, universal, Ex-or, Ex-nor gate using Nand gate only.

Design basic, universal, Ex-or, Ex-nor gate using Nand gate only.
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Design basic, universal, Ex-or, Ex-nor gate using Nand gate only.

Design basic, universal, Ex-or, Ex-nor gate using Nand gate only.
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OR GATE

OR GATE
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verify truth table of basic gates ,buffer and universal gate.

verify truth table of basic gates ,buffer and universal gate.
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2-bit counter with display

2-bit counter with display
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4 X 1 MUX using gates

4 X 1 MUX using gates
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16 X 1 MUX using only 2 X 1 MUXs

16 X 1 MUX using only 2 X 1 MUXs
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HA using HS and NOT

HA using HS and NOT
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2 X 1 MUX

2 X 1 MUX
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1 X 2 DMUX

1 X 2 DMUX
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JK Flip Flops

JK Flip Flops
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Two input AND gate using MUXs

Two input AND gate using MUXs
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Hald adder using DMUXs

Hald adder using DMUXs
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2-bit counter with display

2-bit counter with display
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FLIP FLIPS CONVERSION

FLIP FLIPS CONVERSION
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Design and verify 4-bit Asychronous up / down couter

Design and verify 4-bit Asychronous up / down couter
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asynchronous decade counter

asynchronous decade counter
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SR flip- flop using NAND

SR flip- flop using NAND
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Untitled

Untitled
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XOR USING FIVE NAND

XOR USING FIVE NAND
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XOR USING NAND

XOR USING NAND
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Untitled

Untitled
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ASSICIATIVE LAW FOR AND LOGIC

ASSICIATIVE LAW FOR AND LOGIC
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Absorption law for OR AND LOGIC

Absorption law for OR AND LOGIC
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IDEMPOTENT LAW FOR OR LOGIC

IDEMPOTENT LAW FOR OR LOGIC
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COMPLEMENTATION LAW FOR OR LOGIC

COMPLEMENTATION LAW FOR OR LOGIC
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IDEMPOTENT LAW FOR AND LOGIC

IDEMPOTENT LAW FOR AND LOGIC
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COMPLEMENT LAW FOR AND LOGIC

COMPLEMENT LAW FOR AND LOGIC
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TWO LEVEL IMPLEMENTATION OF POS FORM

TWO LEVEL IMPLEMENTATION OF POS FORM
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2-bit counter with display

2-bit counter with display
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AND GATE

AND GATE
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OR GATE

OR GATE
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NAND

NAND
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NOR

NOR
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EX OR AS NOT AND BUFFER

EX OR AS NOT AND BUFFER
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XOR AS NOT

XOR AS NOT
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DEMORGAN FIRST LAW

DEMORGAN FIRST LAW
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DEMORGAN SECOND LAW

DEMORGAN SECOND LAW
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THREE INPUT AND USING TWO INPUT AND

THREE INPUT AND USING TWO INPUT AND
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Binary to BCD

Binary to BCD
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BCD TO BINARY

BCD TO BINARY
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BINARY TO GRAY

BINARY TO GRAY
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GRAY TO BINARY

GRAY TO BINARY
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Untitled

Untitled
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2 BIT COMPARATOR

2 BIT COMPARATOR
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THREE BIT EVEN PARITY GENERATOR

THREE BIT EVEN PARITY GENERATOR
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CC-1

CC-1
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CC-2 NAND

CC-2 NAND
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CC-3 NOR

CC-3 NOR
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mux1

mux1
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mux2

mux2
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MUX3

MUX3
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mux4

mux4
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mux5

mux5
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mux7

mux7
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MUX6

MUX6
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Untitled

Untitled
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HS USING BASIC GATES

HS USING BASIC GATES
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HS NOR NOR

HS NOR NOR
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HS USING XOR, NANAD

HS USING XOR, NANAD
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FS USIN BASIC GATES

FS USIN BASIC GATES
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FS USING TWO HS

FS USING TWO HS
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FS USING NANND

FS USING NANND
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FS USING NAND-NAND GATES

FS USING NAND-NAND GATES
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FS USING NOR NOR

FS USING NOR NOR
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OCTAL TO BINAY

OCTAL TO BINAY
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XOR USING BASIC GATES

XOR USING BASIC GATES
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HA USING NOR NOR

HA USING NOR NOR
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D F/F USING NAND

D F/F USING NAND
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2-bit asynchronous counter

2-bit asynchronous counter
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DISTRIBUTION LAW OR OVER AND

DISTRIBUTION LAW OR OVER AND
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HS USING NAND

HS USING NAND
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ABSORPTION LAW FOR OR AND LOGIC

ABSORPTION LAW FOR OR AND LOGIC
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FOUR INPUT NAND USING TWO INPUT NAND

FOUR INPUT NAND USING TWO INPUT NAND
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4 X 1 MUX using gates

4 X 1 MUX using gates
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SR flip- flop using NAND

SR flip- flop using NAND
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Design basic, universal, Ex-or, Ex-nor gate using Nand gate only.

Design basic, universal, Ex-or, Ex-nor gate using Nand gate only.
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Full Adder

Full Adder
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3-bit Asynchronous up/down counter using control switch

3-bit Asynchronous up/down counter using control switch
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4-bit synchronous counter

4-bit synchronous counter
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4 X 1 MUX using gates

4 X 1 MUX using gates
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project.name
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SR flip- flop using NAND

SR flip- flop using NAND
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project.name
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Design basic, universal, Ex-or, Ex-nor gate using Nand gate only.

Design basic, universal, Ex-or, Ex-nor gate using Nand gate only.
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project.name
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Design basic, universal, Ex-or, Ex-nor gate using Nand gate only.

Design basic, universal, Ex-or, Ex-nor gate using Nand gate only.
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project.name
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FULL ADDER USING XOR AND NAND GATES

FULL ADDER USING XOR AND NAND GATES
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TWO LEVEL IMPLEMENTATION OF SOP

TWO LEVEL IMPLEMENTATION OF SOP
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4 X 1 MUX using gates

4 X 1 MUX using gates
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2-bit counter with display

2-bit counter with display
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SR flip- flop using NAND

SR flip- flop using NAND
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16 X 1 MUX using only 2 X 1 MUXs

16 X 1 MUX using only 2 X 1 MUXs
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Branch name

Branch name
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FLIP FLIPS CONVERSION

FLIP FLIPS CONVERSION
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Design and verify 4-bit Asychronous up / down couter

Design and verify 4-bit Asychronous up / down couter
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4-bit ripple counter

4-bit ripple counter
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asynchronous decade counter

asynchronous decade counter
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Asynchronous MOD-5 Counter

Asynchronous MOD-5 Counter
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3-bit Asynchronous up/down counter using control switch

3-bit Asynchronous up/down counter using control switch
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4-bit synchronous counter

4-bit synchronous counter
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2-bit synchronous counter

2-bit synchronous counter
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Dr Vijay Singh Bist is not a collaborator of any project.

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