Member since: 4 years
Educational Institution: GLA University, Mathura
Country: India
SIPO
SIPOSeven Segment
Seven SegmentFlip-Flops using NAND Gate
Flip-Flops using NAND GateSynchronous
SynchronousJK Flip flops
JK Flip flopsCounter
CounterUniversal Gate
Universal GateFull Subtractor
Full SubtractorHalf Adder Circuit
Half Adder Circuit4Bit Adder
4Bit Adder3 Bit SISO
3 Bit SISONAND Gate
NAND GateMOD4 Synchronous Up Counter
MOD4 Synchronous Up CounterHalf Adder using Basic Gates
Half Adder using Basic GatesSeven Segment
Seven Segment4Bit PIPO Shift Register
4Bit PIPO Shift RegisterLatch
LatchUniversal Gate
Universal GateHalf Subtracter
Half Subtracter4Bit Subtractor
4Bit SubtractorALU Using Mux
ALU Using Mux4Bit SIPO Shift Register
4Bit SIPO Shift RegisterFull Adder
Full Adder