project.name

ADITYA SHARMA

Member since: 4 years

Educational Institution: GLA University, Mathura

Country: India

SIPO

SIPO
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Seven Segment

Seven Segment
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Flip-Flops using NAND Gate

Flip-Flops using NAND Gate
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Synchronous

Synchronous
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JK Flip flops

JK Flip flops
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Counter

Counter
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Universal Gate

Universal Gate
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Full Subtractor

Full Subtractor
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Half Adder Circuit

Half Adder Circuit
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4Bit Adder

4Bit Adder
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3 Bit SISO

3 Bit SISO
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NAND Gate

NAND Gate
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MOD4 Synchronous Up Counter

MOD4 Synchronous Up Counter
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Half Adder using Basic Gates

Half Adder using Basic Gates
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Seven Segment

Seven Segment
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4Bit PIPO Shift Register

4Bit PIPO Shift Register
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Latch

Latch
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Universal Gate

Universal Gate
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Half Subtracter

Half Subtracter
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4Bit Subtractor

4Bit Subtractor
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ALU Using Mux

ALU Using Mux
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4Bit SIPO Shift Register

4Bit SIPO Shift Register
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Full Adder

Full Adder
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