project.name

ADITYA SHARMA

Member since: 4 years

Educational Institution: GLA University, Mathura

Country: India

SIPO

SIPO
Public
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Seven Segment

Seven Segment
Public
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Flip-Flops using NAND Gate

Flip-Flops using NAND Gate
Public
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Synchronous

Synchronous
Public
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JK Flip flops

JK Flip flops
Public
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Counter

Counter
Public
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Universal Gate

Universal Gate
Public
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Full Subtractor

Full Subtractor
Public
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Half Adder Circuit

Half Adder Circuit
Public
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4Bit Adder

4Bit Adder
Public
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3 Bit SISO

3 Bit SISO
Public
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NAND Gate

NAND Gate
Public
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MOD4 Synchronous Up Counter

MOD4 Synchronous Up Counter
Public
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Half Adder using Basic Gates

Half Adder using Basic Gates
Public
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Seven Segment

Seven Segment
Public
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4Bit PIPO Shift Register

4Bit PIPO Shift Register
Public
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Latch

Latch
Public
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Universal Gate

Universal Gate
Public
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Half Subtracter

Half Subtracter
Public
project.name

4Bit Subtractor

4Bit Subtractor
Public
project.name

ALU Using Mux

ALU Using Mux
Public
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4Bit SIPO Shift Register

4Bit SIPO Shift Register
Public
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Full Adder

Full Adder
Public
project.name
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