project.name

Gerold Bausch

Member since: 3 years

Educational Institution: Leipzig University of Applied Sciences

Country: Germany

Halb-Addierer

Halb-Addierer
Public
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4-Bit Addierer

4-Bit Addierer
Public
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D-FlipFlop

D-FlipFlop
Public
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SR Latch

SR Latch
Public
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Shift Register (Right)

Shift Register (Right)
Public
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Register

Register
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Voll-Addierer

Voll-Addierer
Public
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BitSequenceDetector_Verilog

BitSequenceDetector_Verilog
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BitSequenceDetector

BitSequenceDetector
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6Bit-Speicher_FULL

6Bit-Speicher_FULL
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Verilog_FullAdder

Verilog_FullAdder
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6Bit-Speicher_READ+WRITE

6Bit-Speicher_READ+WRITE
Public
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6Bit-Speicher_WRITE

6Bit-Speicher_WRITE
Public
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D-FlipFlop

D-FlipFlop
Public
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Verilog_AND-Gate

Verilog_AND-Gate
Public
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SR Latch NOR-Gates

SR Latch NOR-Gates
Public
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6Bit-Speicher_READ

6Bit-Speicher_READ
Public
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R-S-Latch

R-S-Latch
Public
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Parallel-access shift register

Parallel-access shift register
Public
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3-Bit-Aufwärtszähler (Template)

3-Bit-Aufwärtszähler (Template)
Public
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Frequenzteiler_Simple

Frequenzteiler_Simple
Public
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Counter_Down

Counter_Down
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4-Bit Voll-Addierer

4-Bit Voll-Addierer
Public
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D Latch

D Latch
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