PARALLEL IN SERIAL OUT

SR flip flop

JK flip flop

study of logic gates

study of logic gates

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER

D flip flop

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR

DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

D flip flop

T FLIP FLOP

HALF ADDER

HALF ADDER

FULLADDERUSINGTWOHALFADDER

HALF SUBTRACTOR

FULL SUBTRACTOR

DESIGN AND IMPLEMENTATION OF CODE CONVERTORS

JK flip flop

T flip flop

Untitled

Untitled

STUDY OF LOGIC GATES

SIMULATION OF COMBINATIONAL CIRCUITS USING VERILOG HDL

SHIFT REGISTER -SERIAL IN PARALLEL OUT

SHIFT REGISTERS :SERIAL -IN SERIAL -OUT

DESIGN AND IMPLEMENTATION OF CODE CONVERTORS

STUDY OF LOGIC GATES

Untitled

VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES

HALF ADDER

SYNCHRONOUS 3 BIT UP COUNTER USING T FLIP FLOPS