MULTIPLEXER

BCD to Excess -3 Code Convertor

JK FLIPFLOP

down counter

Aishwarya E

T FLIPFLOP

Aishwarya E

Aishwarya E

Half adder

Logic gates basis

OR gate

Aishwarya E

theorem 2

Aishwarya E

Aishwarya E

Aishwarya E

X-OR GATE

Binary to Gray code convertor

THEOREM 5

And Gate

Theorem 1.1

Theorem 6

Aishwarya E

Theorem 2.1

Aishwarya E

3 - INPUT NAND GATE

MURAI REDDY SUDARSAN

theorem 4.2

Design of Full Subtractor

T FLIPFLOP

2-bit magnitude comparator

EXP NO:5 Design and Implementation of Code Convertors

Theorem 3

NOT GATE

DEMUTIPLEXER

JK FLIPFLOP

FULL SUBTRACTOR

FULL ADDER

4-bit synchronous counter using JK flipflop

ODD PARITY CHECKER

Even parity checker

3-bit odd parity

SERIAL IN PARALLEL OUT

PARALLEL IN SERIAL OUT

Serial in serial out

NAND GATE (2 I/P)

Theorem 4.1

Excess -3 to BCD Code Convertor

HALF SUBTRACTOR

Aishwarya E