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viknash

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EXPERIMENT 1Aii 5-INPUT AND GATE

EXPERIMENT 1Aii 5-INPUT AND GATE
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EXPT 2A NAND CIRCUIT

EXPT 2A NAND CIRCUIT
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expt2 part b

expt2 part b
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EXPERIMENT 1A INVERTER

EXPERIMENT 1A INVERTER
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EXPT 2 AND-OR CIRCUIT

EXPT 2 AND-OR CIRCUIT
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EXPERMENT 1B NAND & NOR

EXPERMENT 1B NAND & NOR
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EXPERIMENT 1Aiii OR GATE INPUT

EXPERIMENT 1Aiii OR GATE INPUT
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EXP 3A D FF

EXP 3A D FF
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LAB TEST

LAB TEST
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EXPT 3B JK FF

EXPT 3B JK FF
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EXPERIMENT 1Aii

EXPERIMENT 1Aii
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Untitled

Untitled
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EXPERIMENT 1Aii 3 INPUT AND GATE

EXPERIMENT 1Aii 3 INPUT AND GATE
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EXPERIMENT 1Ai inverter

EXPERIMENT 1Ai inverter
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