project.name

S.Ramya Raja Yazhini

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

EXOR Gate

EXOR Gate
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TFF Using SRFF

TFF Using SRFF
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1:16 demux

1:16 demux
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Boolean Laws Of Addition

Boolean Laws Of Addition
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Half Adder

Half Adder
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Magnitude Comparator(1 bit, 2 bit)

Magnitude Comparator(1 bit, 2 bit)
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Parity Checker and Generator

Parity Checker and Generator
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Full AdderII

Full AdderII
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TFF Using JKFF

TFF Using JKFF
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JK-FF using NAND Gates

JK-FF using NAND Gates
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T-FF using NAND Gates

T-FF using NAND Gates
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Boolean Laws Of Multiplication

Boolean Laws Of Multiplication
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Shift Registers

Shift Registers
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SRFF

SRFF
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OR Gate

OR Gate
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Consensus Theorem

Consensus Theorem
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Commutative Laws

Commutative Laws
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T-FF

T-FF
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DFF from SRFF

DFF from SRFF
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NAND Gate

NAND Gate
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NOT Gate

NOT Gate
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AND Gate

AND Gate
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D-FF

D-FF
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JK-FF

JK-FF
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EXNOR Gate

EXNOR Gate
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Half Subtractor

Half Subtractor
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Absorption Laws

Absorption Laws
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Full Adder

Full Adder
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DeMorgan's Theorem

DeMorgan's Theorem
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Associative Laws

Associative Laws
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Code ConvertersII

Code ConvertersII
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Commutative Law Of Addition

Commutative Law Of Addition
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DFF using JKFF

DFF using JKFF
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Ripple Up Counter with Decoded Output

Ripple Up Counter with Decoded Output
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Full Subtrator

Full Subtrator
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Counters

Counters
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Exp 11

Exp 11
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JKFF Using TFF

JKFF Using TFF
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NOR Gate

NOR Gate
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D-FF using NAND Gates

D-FF using NAND Gates
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Shift Registers

Shift Registers
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Distributive Laws

Distributive Laws
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NAND Based SR FF

NAND Based SR FF
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Encoder(2x1,4x2)

Encoder(2x1,4x2)
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DFF Using TFF

DFF Using TFF
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Code Converters(Binary,Gray)

Code Converters(Binary,Gray)
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Full SubtractorII

Full SubtractorII
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S.Ramya Raja Yazhini is not a collaborator of any project.

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