project.name

Rathpisey Heng

Member since: 4 years

Educational Institution: Institute of Technology of Cambodia

Country: Cambodia

RAM

RAM
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project.name
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Adder

Adder
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project.name
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2-bit syn counter

2-bit syn counter
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project.name
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4bitadder

4bitadder
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project.name
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Untitled

Untitled
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project.name
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Simple counter

Simple counter
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project.name
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Memory Test

Memory Test
Public
project.name
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Chapter 4 Examples

Chapter 4 Examples
Public
project.name
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I3 TP3 2020

I3 TP3 2020
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project.name
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Untitled

Untitled
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project.name
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Timer___Vichea

Timer___Vichea
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project.name
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TP6

TP6
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project.name
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Testresit

Testresit
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project.name
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CSC4536

CSC4536
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project.name
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test jk

test jk
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project.name
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Lab 5

Lab 5
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project.name
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example1

example1
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project.name
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Untitled

Untitled
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project.name
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Ring Counter

Ring Counter
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project.name
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Binary to BCD

Binary to BCD
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project.name
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Asyn Counte

Asyn Counte
Public
project.name
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Error detection and correction

Error detection and correction
Public
project.name
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Clock and Counters

Clock and Counters
Public
project.name
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TP 5

TP 5
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project.name
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Counter

Counter
Public
project.name
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Untitled

Untitled
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project.name
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I3 TP3 2020

I3 TP3 2020
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project.name
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Decade Counter

Decade Counter
Public
project.name
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Clock and Counters

Clock and Counters
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project.name
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Read write op using RAM IC

Read write op using RAM IC
Public
project.name
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Untitled

Untitled
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project.name
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GIC2324-CSLProject-5A-CPU

GIC2324-CSLProject-5A-CPU
Public
project.name
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RAM(32words x 10size)

RAM(32words x 10size)
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project.name
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CPU

CPU
Public
project.name
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Error

Error
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project.name
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Final_exam rebuild

Final_exam rebuild
Public
project.name
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Final exam

Final exam
Public
project.name
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d flipflop

d flipflop
Public
project.name
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4-Bit Synchronous Decade Counter

4-Bit Synchronous Decade Counter
Public
project.name
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Untitled

Untitled
Public
project.name
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TP05

TP05
Public
project.name
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GIC2324-CSLProject-5A-CPU

GIC2324-CSLProject-5A-CPU
Public
project.name
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Re-exam cls 2

Re-exam cls 2
Public
project.name
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Untitled

Untitled
Public
project.name
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TimedTraffic

TimedTraffic
Public
project.name
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Mini_project_Chheng_Sophin

Mini_project_Chheng_Sophin
Public
project.name
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test_CPU_project

test_CPU_project
Public
project.name
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CPU

CPU
Public
project.name
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LogicMiniProject-Group10/ Name Timer

LogicMiniProject-Group10/ Name Timer
Public
project.name
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Project1-CPU

Project1-CPU
Public
project.name
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RGB LED Matrix

RGB LED Matrix
Public
project.name
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LogicMiniProject-Group10/ Name Stop_Watch

LogicMiniProject-Group10/ Name Stop_Watch
Public
project.name
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CSC4536-new

CSC4536-new
Public
project.name
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ECE 265 Lab 6 : 3-Step Unlock

ECE 265 Lab 6 : 3-Step Unlock
Public
project.name
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Half and Full Subtractor

Half and Full Subtractor
Public
project.name
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LogicMiniProject-Group10/ Name Stop_Watch

LogicMiniProject-Group10/ Name Stop_Watch
Public
project.name
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TimedTraffic

TimedTraffic
Public
project.name
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Compare A and B

Compare A and B
Public
project.name
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No result image
Rathpisey Heng doesn't have any favourites.

Error detection and correction

Error detection and correction
Public
project.name
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7 segments display

7 segments display
Public
project.name
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Binary to BCD

Binary to BCD
Public
project.name
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I3 TP2 2020

I3 TP2 2020
Public
project.name
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TP4

TP4
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project.name
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I3 TP1 2020

I3 TP1 2020
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project.name
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test

test
Public
project.name
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BCD to Binary

BCD to Binary
Public
project.name
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I3 TP3 2020

I3 TP3 2020
Public
project.name
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mini computer

mini computer
Public
project.name
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LengBuntith_TP1

LengBuntith_TP1
Public
project.name
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TP02

TP02
Public
project.name
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TP2

TP2
Public
project.name
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f(A,B,C)

f(A,B,C)
Public
project.name
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f(d,e,f)

f(d,e,f)
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project.name
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HeangSopagna-ITC-CSL-TP5

HeangSopagna-ITC-CSL-TP5
Public
project.name
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HeangSopagna-ITC-CSL-TP6

HeangSopagna-ITC-CSL-TP6
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project.name
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TP5

TP5
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project.name
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testing

testing
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project.name
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Untitled

Untitled
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project.name
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test1

test1
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project.name
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timer__

timer__
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project.name
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Timer___Vichea

Timer___Vichea
Public
project.name
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Mini_project_Chheng_Sophin

Mini_project_Chheng_Sophin
Public
project.name
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FINAL EXAM

FINAL EXAM
Public
project.name
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LogicMiniProject-Group10/ Name Timer

LogicMiniProject-Group10/ Name Timer
Public
project.name
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LogicMiniProject-Group10/ Name Stop_Watch

LogicMiniProject-Group10/ Name Stop_Watch
Public
project.name
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LogicMiniProject-Group10/ Name Simple_watch

LogicMiniProject-Group10/ Name Simple_watch
Public
project.name
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ITC-CSL-LogicMiniProject-Group4

ITC-CSL-LogicMiniProject-Group4
Public
project.name
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Re-exam cls 2

Re-exam cls 2
Public
project.name
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Re-Exam Exercise 5

Re-Exam Exercise 5
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project.name
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Re-Exam Exercise 4

Re-Exam Exercise 4
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project.name
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Hok_Kolboth_Exercise_5

Hok_Kolboth_Exercise_5
Public
project.name
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Re-Exam_BUN_Arya

Re-Exam_BUN_Arya
Public
project.name
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Final_exam rebuild

Final_exam rebuild
Public
project.name
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Final exam

Final exam
Public
project.name
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GIC2122-CSLProject-Group9 Digital Clock

GIC2122-CSLProject-Group9 Digital Clock
Public
project.name
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Traffic Light system

Traffic Light system
Public
project.name
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Digital Clock (Group12)

Digital Clock (Group12)
Public
project.name
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Final_Project

Final_Project
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project.name
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Traffic light system V3

Traffic light system V3
Public
project.name
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CSL2 - Project SAP Latest

CSL2 - Project SAP Latest
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project.name
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Traffic Light

Traffic Light
Public
project.name
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traffic light with left turn

traffic light with left turn
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project.name
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CPU

CPU
Public
project.name
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Traffic Light

Traffic Light
Public
project.name
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8 Bit Central Processing Unit

8 Bit Central Processing Unit
Public
project.name
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Traffic light

Traffic light
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project.name
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Traffic light

Traffic light
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project.name
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cpu

cpu
Public
project.name
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TrafficLight

TrafficLight
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project.name
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CPU

CPU
Public
project.name
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GIC2324-CSLProject-A7-TRAFFIC LIGHT

GIC2324-CSLProject-A7-TRAFFIC LIGHT
Public
project.name
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GIC2324-CSLProject-A7-CPU

GIC2324-CSLProject-A7-CPU
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project.name
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2024_CSL_Project1_GroupD5

2024_CSL_Project1_GroupD5
Public
project.name
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2024_CSL_Project2_GroupD5

2024_CSL_Project2_GroupD5
Public
project.name
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