In this FPGA design assignment, we will apply our general design workflow to hardware designs via Verilog. 

Recall the design workflow:

1. Define the problem
2. Work examples of the problem
3. Draw a general system-level diagram of a solution
4. Implement the solution
5. Test the solution

Note that these symbols are different than what you would normally write on paper, so be careful!

Your design activity is to implement a solution that solves the following problem, with an implementation in Verilog.  You will submit your solution here on Canvas by submitting your Verilog-based .v file.  Please submit files individually.

You can choose to use either the "module instantiation" method of wiring within Verilog, or you can use "direct assignment".  If you use direct assignment, note that the Boolean operators in Verilog are different than the symbols we use for Boolean operators when writing equations on paper.

In Verilog, the following bitwise Boolean operators exist in the "direct assignment" method:

Here's the design problem:

• We are creating an alarm module to detect when someone is stealing our lunch.  Our lunchbox has three sensors (A, B, and C) on it. 
• If both sensors A and C report a problem without sensor B reporting a problem, then the alarm will be triggered. 
• If both sensors B and C report a problem without sensor A reporting a problem, then the alarm will be triggered.
• If sensor A reports a problem, but neither sensors B and C report a problem, then the alarm will be triggered.
• If all three sensors report a problem, do NOT trigger the alarm.

To solve this design problem:

1. Think about what your inputs and your output(s) for the module are.  What represents each sensor A, B, and C?  Can you relate reporting problems to particular logic values (either 0 or 1)?
   Hint: there is only one output for this particular problem and it is only one-bit wide -- what is it?
2. Write the truth table or K-map based on your inputs and output are.
3. Write the function's equation based on your truth table (sum of products representation) or K-map (fully simplified equation).
4. Implement and simulate your equation in CircuitVerse against the design problem cases to make sure it is exactly what you intended.
   Download two images: one image showing when an alarm is supposed to be triggered, and one image showing when an alarm is not supposed to be triggered.
5. Create a new Verilog file named "alarm.v" (make sure you have the .v extension) in Visual Studio Code or your preferred text editor.
6. Declare the alarm module with the inputs and outputs that you think it should have.
7. Then, assign the output based on the inputs using the equation you created in step 3.
8. Do not forget to write "endmodule" at the end of your alarm.v file.

1. Submit your alarm.v file and your images showing the simulation.