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Vikas Srivastava

Member since: 3 years

Educational Institution: AJAY KUMAR GARG ENGINEERING COLLEGE

Country: India

Gen. Register Org.

Gen. Register Org.
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JK Flip Flop

JK Flip Flop
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3- 8 LINE DECODER

3- 8 LINE DECODER
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4 bit register

4 bit register
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4X1 MULTIPLEXER

4X1 MULTIPLEXER
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HALF ADDER SUM CARRY

HALF ADDER SUM CARRY
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8 BIT ALU

8 BIT ALU
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SR Flip Flop

SR Flip Flop
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8-BIT INPUT/OUTPUT SYSTEM

8-BIT INPUT/OUTPUT SYSTEM
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FULL ADDER USING BASIC LOGIC

FULL ADDER USING BASIC LOGIC
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HALF ADDER USING BASIC

HALF ADDER USING BASIC
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HALF ADDER USING UNIVERSAL GATES

HALF ADDER USING UNIVERSAL GATES
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JK Flip Flop

JK Flip Flop
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Vikas Srivastava is not a collaborator of any project.

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