project.name

sivasai

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

sipo

sipo
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4-Bit Synchronous Decade Counter

4-Bit Synchronous Decade Counter
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half adder using basic gates

half adder using basic gates
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4 : 1 Demultiplexer

4 : 1 Demultiplexer
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3 bit asynchronous counter

3 bit asynchronous counter
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Untitled

Untitled
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Untitled

Untitled
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8 : 1 Multiplexer (alternative)

8 : 1 Multiplexer (alternative)
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1 : 16 demultiplexer

1 : 16 demultiplexer
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Pipo

Pipo
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SISO

SISO
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sipo

sipo
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Untitled

Untitled
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sipo

sipo
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sipo

sipo
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sipo

sipo
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SIPO

SIPO
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Asynchronous Ripple Counter

Asynchronous Ripple Counter
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Asynchronous Ripple Counter

Asynchronous Ripple Counter
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4-Bit Synchronous Down Counter

4-Bit Synchronous Down Counter
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4-Bit Synchronous Counter

4-Bit Synchronous Counter
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Parity Generator

Parity Generator
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4-bit parallel adder/subtractor

4-bit parallel adder/subtractor
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Parity Checker and generator

Parity Checker and generator
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3 bit asynchronous counter

3 bit asynchronous counter
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4-Bit Synchronous Up Counter

4-Bit Synchronous Up Counter
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2 bit asynchronous down counter

2 bit asynchronous down counter
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shift registers (sipo)

shift registers (sipo)
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2 bit asynchronous up counter

2 bit asynchronous up counter
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Half-subtractor

Half-subtractor
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Full Adder From 2 half Adders

Full Adder From 2 half Adders
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Full Adder

Full Adder
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full subtract

full subtract
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4 : 1 multiplexer

4 : 1 multiplexer
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Shift Register - PIPO Mode

Shift Register - PIPO Mode
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Shift Register PISO

Shift Register PISO
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sivasai is not a collaborator of any project.

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