You must login before you can post a comment.
Author: Anish Mathew Oommen P
Project access type: Public
Description:
The external clock is directly connected to all J-K Flip-flops at the same time in a parallel way not sequential. If we see the circuit, the first flip-flop, JK-1 which is the least significant bit in this 4-bit synchronous counter, is connected to a Logic 1 external input via J and K pin. According to this connection, HIGH logic across the Logic 1 signal, toggles the state of first flip-flop on every clock pulse.
Created: Nov 18, 2020
Updated: Jan 27, 2021
Comments