project.name

Ayushi

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

full adder

full adder
Public
project.name

4 registers

4 registers
Public
project.name

OPEN ENDED EXPERIMENT

OPEN ENDED EXPERIMENT
Public
project.name

2 BIT MAGNITUDE COMPARATOR

2 BIT MAGNITUDE COMPARATOR
Public
project.name

4:1 mux using logic gates

4:1 mux using logic gates
Public
project.name

Srisha 2 bit comparator

Srisha 2 bit comparator
Public
project.name

8 registers

8 registers
Public
project.name

8 BIT ALU

8 BIT ALU
Public
project.name

4 BIT BCD ADDER

4 BIT BCD ADDER
Public
project.name

Priority encoders

Priority encoders
Public
project.name

common bus system using MUX

common bus system using MUX
Public
project.name

8bit alu

8bit alu
Public
project.name
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Ayushi is not a collaborator of any project.