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Ayushi

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

full adder

full adder
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4 registers

4 registers
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OPEN ENDED EXPERIMENT

OPEN ENDED EXPERIMENT
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2 BIT MAGNITUDE COMPARATOR

2 BIT MAGNITUDE COMPARATOR
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4:1 mux using logic gates

4:1 mux using logic gates
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Srisha 2 bit comparator

Srisha 2 bit comparator
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8 registers

8 registers
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8 BIT ALU

8 BIT ALU
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Priority encoders

Priority encoders
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common bus system using MUX

common bus system using MUX
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4 BIT BCD ADDER

4 BIT BCD ADDER
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8bit alu

8bit alu
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Ayushi is not a collaborator of any project.

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