4-Bit Synchronous Up Counter
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Author: Ruiter Braga Caldas

Forked from: Ayman Nasr/4-Bit Synchronous Up Counter

Project access type: Public


The external clock is directly connected to all J-K Flip-flops at the same time in a parallel way not sequential. If we see the circuit, the first flip-flop, JK-1 which is the least significant bit in this 4-bit synchronous counter, is connected to a Logic 1 external input via J and K pin. According to this connection, HIGH logic across the Logic 1 signal, toggles the state of first flip-flop on every clock pulse.

Created: May 11, 2021

Updated: May 11, 2021


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